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Si3038
GL O B A L M C ' 9 7 SI L I C O N DAA
Features
Complete DAA includes: AC'97 2.1 Compliant Primary or Secondary Codec Global Phone Line Interface Compliant with FCC, CTR21, JATE, and Other PTTs 84 dB Dynamic Range TX/RX Paths 3.3 V or 5 V Power Supply Greater than 3000 V Isolation Integrated Ring Detector Wake-Up On Ring Caller ID Support Integrated Analog Front End 2- to 4-Wire Hybrid Low-Power Standby Mode Low Profile SOIC Packages Patented ISOcapTM Technology
Ordering Information: See page 59.
Applications
Software Modems Audio/Telephony Sub-Systems Audio/Modem Riser Cards (AMR) Mobile Daughter Cards (MDC) Mini-PCI Cards
Pin Assignments
Si3024 (SOIC)
MCLK/XIN XOUT BIT_CLK VD SDA TA _IN SDA TA _OUT SY NC RESET 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GPIO_A GPIO_B ID1 VA GND C1A ID0 A OUT
Description
The Si3038 is an integrated direct access arrangement (DAA) chipset that provides a digital, programmable line interface to meet global telephone line requirements. Available in two 16-pin small outline packages (AC'97 interface on Si3024 and phone-line interface on Si3014), the chipset eliminates the need for an analog front end (AFE), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3038 dramatically reduces the number of discrete components and cost required to achieve compliance with global regulatory requirements. The Si3024 complies with the AC'97 2.1 specification.
Si3024 (TSSOP)
SDA TA _IN SDA TA _OUT SY NC RESET A OUT ID0 C1A GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VD BIT_CLK XOUT MCLK/XIN GPIO_A GPIO_B ID1 VA
Functional Block Diagram
Si3024
XOUT MCLK/XIN RESET BIT_CLK SYNC SDATA_IN SDATA_OUT AC'97 Digital Interface Clock Hybrid and DC Termination
Si3014
Si3014 (SOIC or TSSOP)
RX
QE2
FILT FILT2 REF DCT VREG VREG2 REXT REXT2 RNG1 RNG2 QB QE QE2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
FILT2 FILT RX REXT REXT2 REF V REG2 V REG
DCT IGND C1B RNG1 RNG2 QB QE
Isolation Interface
Isolation Interface
ID0 ID1 G PIO_A G PIO_B Control Interface
Ring Detect
Off-Hook
US Patent # 5,870,046 US Patent # 6,061,009 Other Patents Pending
Si3038-DS201
Rev. 2.01 9/01
Copyright (c) 2001 by Silicon Laboratories
Si3038
2
Rev. 2.01
Si3038 TABLE O F CONTENTS
Section Page
4 16 17 19 20 22 22 22 23 23 24 24 24 25 25 26 26 26 27 28 28 28 29 29 29 29 29 30 30 30 30 30 30 31 36 37 38 53 54 55 57 59 60 61 64
3
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Termination Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringer Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up on Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Billing Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Si3024 as Secondary Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Si3024 as Primary MC'97 Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Si3024 Connection to the Digital AC'97 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resetting Si3038 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC-Link Digital Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Codec Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC-Link Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A--UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix B--CISPR22 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si3024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions--Si3014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 2.01
Si3038
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter1 Ambient Temperature3 Si3024 Supply Voltage, Analog Si3024 Supply Voltage, Digital4 Si3024 Supply Voltage, Digital
4
Symbol TA VA VD VD
Test Condition K-Grade
Min2 0 4.75
Typ 25 5.0 5.0 3.3
Max2 70 5.25 5.25 3.6
Unit C V V V
VA = 5 V VA = Charge Pump
4.75 3.0
Notes: 1. The Si3038 specifications are guaranteed when the typical application circuit (including component tolerances) of Figure 19 on page 16 and any Si3024 and Si3014 are used. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. 3. The temperature specifications are guaranteed when using the typical application circuit on a 4 sq. in. minimum FR4 PCB. For other materials and smaller form factors, heat dissipation factors may apply. Contact Silicon Laboratories for more details. 4. The digital supply, VD, can operate from either 3.3 V or 5.0 V. The Si3024 supports interface to 3.3 V logic when operating from 3.3 V. 3.3 V operation applies to both the AC'97 Digital Interface and the digital signals RESET, ID0, and ID1.
4
Rev. 2.01
Si3038
Table 2. Loop Characteristics
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 0 to 70C, See Figure 1)
Parameter DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage On Hook Leakage Current Operating Loop Current Operating Loop Current DC Ring Current DC Ring Current Ring Detect Voltage Ring Detect Voltage Ring Frequency Ringer Equivalence Number Ringer Equivalence Number
2 2 1 1
Symbol VTR VTR VTR VTR VTR VTR VTR VTR ILK ILP ILP
Test Condition IL = 20 mA, ACT=1 DCT=11 (CTR21) IL = 42 mA, ACT=1 DCT=11 (CTR21) IL = 50 mA, ACT=1 DCT=11 (CTR21) IL = 60 mA, ACT=1 DCT=11 (CTR21) IL = 20 mA, ACT=0 DCT=01 (Japan) IL = 100 mA, ACT=0 DCT=01 (Japan) IL = 20 mA, ACT=0 DCT=10 (FCC) IL = 100 mA, ACT=0 DCT=10 (FCC) VTR = -48V FCC/JATE Mode CTR21 Mode w/o Caller ID with Caller ID
Min -- -- -- 40 -- 11 -- 12 -- 13 13 -- -- 11 17 15 -- --
Typ -- -- -- -- -- -- -- -- -- -- -- -- 450 -- -- -- -- 0.8
Max 7.5 14.5 40 -- 6.0 -- 7.5 -- 1 120 60 20 -- 22 33 68 0.2 --
Unit V V V V V V V V A mA mA A A VRMS VRMS Hz
VRD VRD FR REN REN
RT = 0 RT = 1 w/o Caller ID with Caller ID
Notes: 1. The ring signal is guaranteed not to be detected below the minimum and is guaranteed to be detected above the maximum. 2. C15, R14, Z2, and Z3 not installed. See "Ringer Impedance" on page 25.
TIP
+ 600
Si3014
V TR 10 F -
IL
RING
Note: The remainder of the circuit is identical to the one shown in Figure 19 on page 16.
Figure 1. Test Circuit for Loop Characteristics
Rev. 2.01
5
Si3038
Table 3. DC Characteristics, VD = + 5 V
(VA = 4.75 to 5.25 V, VD = 4.75 to 5.25 V, TA = 0C to 70C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Power Supply Current, Analog Power Supply Current, Digital Total Supply Current, Sleep Mode
Symbol VIH VIL VOH VOL IL IA ID IA + ID
Test Condition
Min 3.5 --
Typ -- -- -- -- -- 0.1 14 --
Max -- 0.8 -- 0.4 10 2 17 1.5
Unit V V V V A mA mA mA
IO = -2 mA IO = 2 mA VA pin VD pin
2.4 -- -10 -- -- --
Table 4. DC Characteristics, VD = + 3.3 V
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 0 to 70C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Power Supply Current, Digital Total Supply Current, Sleep Mode
Symbol VIH VIL VOH VOL IL ID IA + ID
Test Condition
Min 2.4 --
Typ -- -- -- -- -- 12 1.5
Max -- 0.8 -- 0.35 10 14.5 3.0
Unit V V V V A mA mA
IO = -2 mA IO = 2 mA VD pin
2.4 -- -10 -- --
6
Rev. 2.01
Si3038
Table 5. AC Characteristics
(VD = 3.0 to 5.25 V, VA = Charge Pump, TA = 0 to 70C)
Parameter Transmit Frequency Response Receive Frequency Response Transmit Full Scale Level1 Receive Full Scale Level1,2 Dynamic Range3 Dynamic Range3 Dynamic Range3 Transmit Total Harmonic Distortion4 Transmit Total Harmonic Distortion4 Receive Total Harmonic Distortion4 Receive Total Harmonic Distortion4 Dynamic Range (call progress AOUT) THD (call progress AOUT) AOUT Full Scale Level AOUT Output Impedance Mute Level (call progress AOUT) Dynamic Range (Caller ID mode) Caller ID Full Scale Level (0 dB gain)
Symbol
Test Condition Low -3 dBFS Corner Low -3 dBFS Corner
Min -- -- -- --
Typ 0 5 1 1 82 83 84 -85 -76 -74 -82 -- 1.0 0.75 VD 10 -- 60 0.8
Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit Hz Hz VPEAK VPEAK dB dB dB dB dB dB dB dB % VPP k dBFS dB VPEAK
VFS VFS DR DR DR THD THD THD THD DRAO THDAO ACT = 0, DCT = 10 (FCC), IL = 100 mA ACT = 0, DCT = 01 (Japan), IL = 20 mA ACT = 1, DCT = 11 (CTR21), IL = 60 mA ACT = 0, DCT = 10 (FCC), IL = 100 mA ACT = 0, DCT = 01 (Japan), IL = 20 mA ACT = 0, DCT = 01 (Japan), IL = 20 mA ACT = 1, DCT = 11 (CTR21), IL = 60 mA VIN = 1 kHz VIN = 1 kHz
-- -- -- -- -- -- -- 60 -- -- -- -90
DRCID VCID
VIN = 1 kHz, -13 dBFS
-- --
Notes: 1. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1 on page 5. 2. Receive full scale level will produce -0.9 dBFS. 3. DR = 20 log |Vin| + 20 log (RMS signal/RMS noise). Measurement bandwidth is 300 to 3400 Hz. Applies to both transmit and receive paths. Vin = 1 kHz, -3 dBFS, Fs = 10300 Hz. 4. THD = 20 log (RMS distortion/RMS signal). Vin = 1 kHz, -3 dBFS, Fs = 10300 Hz.
Rev. 2.01
7
Si3038
Table 6. Absolute Maximum Ratings
Parameter DC Supply Voltage Input Current, Si3024 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Symbol VD, VA IIN VIND TA TSTG Value -0.5 to 6.0 10 -0.3 to (VD + 0.3) -40 to 100 -65 to 150 Unit V mA V C C
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 7. AC Link Timing Characteristics--Cold Reset
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25C, CL = 50 pF)
Parameter RESET Active Low Pulse Width RESET Inactive to BIT_CLK Startup Delay
Symbol Trst_low Trst2clk
Min 1.0 162.8
Typ -- --
Max -- --
Unit s ns
T rst2clk T rst_low RESET
BIT_CLK
Figure 2. Cold Reset Timing Diagram Table 8. AC Link Timing Characteristics--Warm Reset
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25C, CL = 50 pF)
Parameter SYNC Active High Pulse Width SYNC Inactive to BIT_CLK Startup Delay
Symbol Tsync_high Tsync2clk
Min 1.0 162.8
Typ -- --
Max -- --
Unit s ns
T sync_high SYNC BIT_CLK
T sync2clk
Figure 3. Warm Reset Timing Diagram
8
Rev. 2.01
Si3038
Table 9. AC Link Timing Characteristics--Clocks
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25C, CL = 50 pF)
Parameter BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter BIT_CLK High Pulse Width* BIT_CLK low Pulse Width* SYNC Frequency SYNC Period SYNC High Pulse Width SYNC Low Pulse Width
Symbol
Min --
Typ 12.288 81.4 -- 40.7 40.7 48.0 20.8 1.3 19.5
Max -- -- 750 45 45 -- -- -- --
Unit MHz ns ps ns ns kHz s s s
Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low
-- -- 36 36 -- -- -- --
*Note: Worst case duty cycle restricted to 45/55.
T clk_low BIT_CLK T clk_high T clk_period T sync_low
SYNC T sync_high T sync_period
Figure 4. Clocks Timing Diagram
Rev. 2.01
9
Si3038
Table 10. AC Link Timing Characteristics--Data Setup and Hold
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25C, CL = 50 pF)
Parameter Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK
Symbol Tsetup Thold
Min 15.0 5.0
Typ -- --
Max -- --
Unit ns ns
T setup BIT_CLK SYNC SDATA_OUT SDATA_IN T hold
Figure 5. Data Setup and Hold Timing Diagram Table 11. AC Link Rise and Fall Times
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25C, CL = 50 pF)
Parameter BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time
Symbol Triseclk Tfallclk Trisesync Tfallsync Trisedin Tfalldin Trisedout Tfalldout
Min 2 2 2 2 2 2 2 2
Typ -- -- -- -- -- -- -- --
Max 6 6 6 6 6 6 6 6
Unit ns ns ns ns ns ns ns ns
BIT_CLK Trise clk Tfallclk
SDATA_IN Trise din Tfalldin
SYNC Trise sync Tfallsync
SDATA_OUT Trise dout Tfalldout
Figure 6. Signal Rise and Fall Timing Diagram
10
Rev. 2.01
Si3038
Table 12. AC Link Timing Characteristics-- Low Power Mode Timing
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25C, CL = 50 pF)
Parameter End of Slot 2 to BIT_CLK, SDATA_IN Low
Symbol Ts2_pdown
Min --
Typ --
Max 1.0
Unit s
SYNC BIT_CLK SDATA_OUT SDATA_IN
Slot 1 Slot 2
W rite to 0x56
Data MLNK
Don't care
T s2_pdow n
Note: BIT_CLK not to scale
Figure 7. AC-Link Low Power Mode Timing Diagram Table 13. ATE Test Mode
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25C, CL = 50 pF)
Parameter1,2 Setup to rising edge of RESET (also applies to SYNC) Rising edge of RESET to Hi-Z delay
Symbol Tsetup2rst Toff
Min 15.0 --
Typ -- --
Max -- 25.0
Unit ns ns
Notes: 1. All AC link signals are normally low through the trailing edge of RESET. Bringing SDATA_OUT high for the trailing edge of RESET causes AC'97 AC-link outputs to go high impedance, which is suitable for ATE in circuit testing. 2. When the test mode has been entered, AC'97 must be issued another RESET with all AC-link signals low to return to the normal operating mode.
RESET SDATA_OUT T setup2rst SDATA_IN, BIT_CLK T off Hi-Z
Figure 8. ATE Test Mode Timing Diagram
Rev. 2.01
11
Si3038
Table 14. Digital FIR Filter Characteristics--Transmit and Receive
(VD = 3.0 to 3.6 V, VA = Charge Pump, Sample Rate = 8 kHz, TA = 70C)
Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay
Symbol F(0.1 dB) F(3 dB)
Min 0 0 -0.1 -- -74
Typ -- -- -- 4.4 -- 12/Fs
Max 3.3 3.6 0.1 -- -- --
Unit kHz kHz dB kHz dB sec
tgd
--
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 9, 10, 11, and 12.
Table 15. Digital IIR Filter Characteristics--Transmit and Receive
(VD = 3.0 to 3.6 V, VA = Charge Pump, Sample Rate = 8 kHz, TA = 70C)
Parameter Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay
Symbol F(3 dB)
Min 0 -0.2 -- -40
Typ -- -- 4.4 -- 1.6/Fs
Max 3.6 0.2 -- -- --
Unit kHz dB kHz dB sec
tgd
--
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 13, 14, 15, and 16. Figures 17 and 18 show group delay versus input frequency.
12
Rev. 2.01
Si3038
Attenuation--dB
Attenuation--dB
Input Frequency--Hz
Input Frequency--Hz
Figure 9. FIR Receive Filter Response
Figure 11. FIR Transmit Filter Response
Attenuation--dB
Attenuation--dB
Input Frequency--Hz
Input Frequency--Hz
Figure 10. FIR Receive Filter Passband Ripple
Figure 12. FIR Transmit Filter Passband Ripple
For Figures 9-12, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows: F(0.1 dB) = 0.4125 Fs F(- 3 dB) = 0.45 Fs where Fs is the sample frequency.
Rev. 2.01
13
Si3038
Attenuation--dB
Input Frequency--Hz
Attenuation--dB
Input Frequency--Hz
Figure 13. IIR Receive Filter Response
Figure 15. IIR Transmit Filter Response
Attenuation--dB
Input Frequency--Hz
Attenuation--dB
Input Frequency--Hz
Figure 14. IIR Receive Filter Passband Ripple
Figure 16. IIR Transmit Filter Passband Ripple
For Figures 13-16, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows: F(- 3 dB) = 0.45 Fs where Fs is the sample frequency.
14
Rev. 2.01
Si3038
Delay--s
Input Frequency--Hz
Delay--s
Input Frequency--Hz
Figure 17. IIR Receive Group Delay
Figure 18. IIR Transmit Group Delay
Rev. 2.01
15
16
+3.3VD 24.576 MHz C10 C3 C34 Y1 C35 D3 BAV99 Z4 Q4 Q1
Typical Application Circuit
Si3038
No Ground Plane In DAA Section
R5 ID1# U1 1 2 3 4 5 6 7 8 MCLK/XIN XOUT BIT_CLK VD SDATA_IN SDATA_OUT SYNC RESET Si3024 AOUT ID0# C30 R29 R30 D4 BAV99 Z5 C2 Q3 See Note 5 C6 C16 R11 + C14 R13 Z1 C20 GPIO_A GPIO_B ID1 VA GND C1A ID0 AOUT 16 15 14 13 12 11 10 9 U2 Si3012/4 C1 R27 R28 1 2 3 4 5 6 7 8 TSTA/QE2 TX/FILT2 TSTB/DCT NC/FILT IGND RX C1B REXT RNG1 DCT/REXT2 RNG2 NC/REF QB NC/VREG2 QE VREG 16 15 14 13 12 11 10 9 R12 R8 R7 R15 C13 C12 + R1 R24 R4 R21 Q2 R18
BITCLK SDATA_IN SDATA_OUT SYNC RESET#
R2
+
C5 + C23 C22 R19 R17 R16
R6
Rev. 2.01
Note 1: This design targets two basic builds: - An FCC and JATE compliant design using the Si3036 chipset. - A worldwide design using the Si3038 chipset.
C19
C8
R10
L2
FB2
Note 2: R12, R13 and C14 are only required if complex AC termination is used (ACT bit = 1). Note 3: See "Billing Tone Detection" section for optional billing tone filter (Germany, Switzerland, South Africa). Note 4: See Appendix A for applications requiring UL 1950 3rd edition compliance. Note 5: For Si3036 designs R29 is populated with a 0 ohm resistor and R30 is not installed. For Si3038 designs R29 is not installed and R30 is populated with a 0 ohm resistor. Note 6: Refer to Appendix B for information regarding L1 and L2.
C18
R23 C29 D1 C25 RV1 RV2 C11 C28 C9 C24 D2 R22 C7 R9 L1 See Note 6 C4 FB1 C31 C32 J1 1 2 3 4 5 6 RJ-11
Figure 19. Typical Applications Circuit for the Dual Design Si3036 and Si3038
Si3038
Bill of Materials
Table 16. Global Component Values--Si3038 Chipset
Component1
C1,C4 C2,C11,C23,C28,C29,C31,C32 C3 C5 C6,C10,C16 C7,C8 C9 C12 C13 C14 C18,C19 C20 C22 C24,C252 C303 C34,C354 D1,D25 D3,D4 FB1,FB2 L1,L26 Q1,Q3 Q2 Q47 RV1 RV28 R1,R4,R21,R22,R23 R2 R3 R5 R6 R7,R8,R15,R16,R17,R199 R9,R10 R11 R12 R13 R18 R24 R27,R28 R29 R30 U1 U2 Y14 Z1 Z4,Z5
Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9.
Value
150 pF, 3 kV, X7R,20% Not Installed 0.22 F, 16 V, X7R,20% 0.1 F, 50 V, Elec/Tant, 20% 0.1 F, 16 V, X7R, 20% 560 pF, 250 V, X7R, 20% 10 nF, 250 V, X7R, 20% 0.22 F, 16 V, Tant, 20% 0.47 F, 16 V, X7R, 20% 0.68 F, 16 V, X7R/Elec/Tant, 20% 3.9 nF, 16 V, X7R, 20% 0.01 F, 16 V, X7R, 20% 1800 pF, 50 V, X7R, 20% 1000 pF, 3 kV, X7R, 10% Not Installed 33 pF, 16 V, NPO, 5% Dual Diode, 300 V, 225 mA BAV99 Dual Diode, 70 V, 350 mW Ferrite Bead 330 mH, 120 mA, DCR <3 , 10% A42, NPN, 300 V A92, PNP, 300 V BCP56T1, NPN, 60 V, 1/2 W Sidactor, 275 V, 100 A Not Installed Not Installed 402 , 1/16 W, 1% Not Installed 36 k, 1/16 W, 5% 120 k, 1/16 W, 5% 4.87 k, 1/4 W, 1% 56 k, 1/10 W, 5% 10 k, 1/16 W, 1% 78.7 , 1/16 W, 1% 215 , 1/16 W, 1% 2.2 k, 1/10 W, 5% 150 , 1/16 W, 5% 10 , 1/10 W, 5% Not Installed 0 , 1/10 W Si3024 Si3014 24.576 MHz, 18 pF, 50 ppm Zener Diode, 43 V, 1/2 W Zener Diode, 5.6 V, 1/2 W
Supplier(s)
Novacap, Venkel, Johanson, Murata, Panasonic Novacap, Venkel, Johanson, Murata, Panasonic
Novacap, Johanson, Murata, Panasonic
Central Semiconductor Diodes Inc., OnSemiconductor, Fairchild Murata Toko OnSemiconductor, Fairchild OnSemiconductor, Fairchild OnSemiconductor, Fairchild Teccor, ST Microelectronics, Microsemi, TI
Silicon Labs Silicon Labs Vishay, OnSemiconductor, Rohm Diodes Inc., OnSemiconductor, Fairchild
The following reference designators were intentionally omitted: C15, C17, C21, C26, C27, C31-C33, R14, and R20. Y2 class capacitors are needed for the Nordic requirements of EN60950 and may also be used to achieve surge performance of 5 kV or better. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, 10%). Y1, C34, and C35 should be installed if the Si3024 is configured as a primary device. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.) See Appendix B for additional considerations. Q4 may require copper on board to meet 1/2 W power requirement. (Contact transistor manufacturer for details.) RV2 can be installed to improve performance from 2500 V to 3500 V for multiple longitudinal surges (270 V, MOV). The R7, R8, R15 and R16, R17, R19 resistors may each be replaced with a single resistor of 1.62 k, 3/4 W, 1%.
Rev. 2.01
17
Si3038
Table 17. FCC Component Values--Si3036 Chipset
Component1
C1,C42 C2 C3 C5 C6,C10,C16 C9,C28,C29 C11 C123 C7,C8,C13,C14,C18, C19,C20,C22 C233 C24,C25,C31,C322,4 C305 C34,C356 D1,D27 D3,D4 FB1,FB2 L1,L2 Q1,Q3 Q2 Q4 RV1 RV2 R1 R2 R3 R4 ,R18,R21 R5,R6 R7,R8,R113,R12,R13,R15 R16,R17,R19,R24 R9,R10 R22,R23 R27,R28 R29 R30 U1 U2 Y15 Z1 Z4,Z5
3 3
Value
150 pF, 3 kV, X7R,20% Not Installed 0.22 F, 16 V, X7R, 20% 1 F, 16 V, Elec/Tant, 20% 0.1 F, 16 V, X7R, 20% 15 nF, 250 V, X7R, 20% 39 nF, 16 V, X7R, 20% 2.7 nF, 16 V, X7R, 20% Not Installed 0.1 F, 16 V, Elec/Tant/X7R, 20% 1000 pF, 3 kV, X7R, 10% Not Installed 33 pF, 16 V, NPO, 5% Dual Diode, 300 V, 225 mA BAV99 Dual Diode, 70 V, 350 mW Ferrite Bead 0 , 1/10 W A42, NPN, 300 V A92, PNP, 300 V Not Installed Sidactor, 275 V, 100 A MOV, 240 V 51 , 1/2 W, 5% 15 , 1/4 W, 5% Not Installed 301 , 1/10 W, 1% 36 k, 1/10 W, 5% Not Installed 2 k, 1/10 W, 5% 20 k, 1/10 W, 5% 10 , 1/10 W, 5% 0 , 1/10 W Not Installed Si3024 Si3012 24.576 MHz, 18 pF, 50 ppm Zener Diode, 18 V Zener Diode, 5.6 V, 1/2 W
Supplier(s)
Novacap, Venkel, Johanson, Murata, Panasonic
Novacap, Johanson, Murata, Panasonic
Novacap, Venkel, Johanson, Murata, Panasonic Novacap, Venkel, Johanson, Murata, Panasonic Central Semiconductor Diodes Inc., OnSemiconductor, Fairchild Murata OnSemiconductor, Fairchild OnSemiconductor, Fairchild Teccor, ST Microelectronics, Microsemi, TI Panasonic
Silicon Labs Silicon Labs Vishay, OnSemiconductor, Rohm Diodes Inc., OnSemiconductor, Fairchild
Notes: 1. The following reference designators were intentionally omitted: C15, C17, C21, C26, C27, C31-C33, R14, and R20. 2. Y2 class capacitors may also be used to achieve surge performance of 5 kV or better. 3. If JATE support is not required, R21, C12, and C23 may be removed and the following modifications implemented: R21 should be replaced with a 0 resistor or shorted, and R4 should be changed to a 604 , 1/4 W, 1%. 4. Alternate population option is C24, C25 (2200 pF, 3 kV, X7R, 10% and C31, C32 not installed). 5. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, 10%). 6. Y1, C34, and C35 should be installed if the Si3024 is configured as a primary device. 7. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.).
18
Rev. 2.01
Si3038
Analog Output
Figure 20 illustrates an optional application circuit to support the analog output capability of the Si3038 for call progress monitoring purposes. The AOUT level can be set to 0 dB, -6 dB, -12 dB, and mute for both transmit and receive paths through the ATM/ARM bits in register 5Ch. U1 provides a gain of 26 dB. Additional gain adjustments may be made by varying the voltage divider created by R1 and R3.
+5 V C2 AOUT R3 3 2-
+
6 5 4 U1
+
C4
C5 C3 Speaker R2
C1
C6
R1
Figure 20. Optional Connection to AOUT for a Call Progress Speaker
`
Table 18. Component Values--Optional Connection to AOUT
Symbol C1 C2, C3, C5 C4 C6 R1 R2 R3 U1 Value 2200 pF, 16 V, 20% 0.1 F, 16 V, 20% 100 F, 16 V, Elec. 20% 820 pF, 16 V, 20% 10 k, 1/10 W, 5% 10 , 1/10 W, 5% 47 k, 1/10 W, 5% LM386
Rev. 2.01
19
Si3038
Functional Description
The Si3038 is an integrated chipset that provides a lowcost, isolated, silicon-based MC'97-compliant interface to the telephone line. The Si3038 complies with the AC'97 2.1 specification and requires only a few low-cost discrete components to achieve global PTT compliance. The device implements Silicon Laboratories' patented ISOcap technology which offers the highest level of integration by replacing an analog front end (AFE), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid with two 16-pin small outline packages (SOIC). The Si3038 chipset can be fully programmed to meet international requirements and is compliant with FCC, CTR21, JATE, and various other country-specific PTT specifications as shown in Table 19. In addition, the Si3038 has been designed to meet the most stringent worldwide requirements for out-of-band energy, emissions, immunity, lightning surges, and safety. Typical Si3038 designs implement a dual layout (see Figure 19) capable of two population options: FCC Compliant Population--This population option removes the external devices needed to support non-FCC countries. The FCC/JATE DAA Si3036 chipset is used. Globally Compliant Population--This population option targets global DAA requirements. This Si3038 international DAA chipset is populated, and the external devices required for the FCC-only population option are removed.
Table 19. Country Specific Register Settings
Register Country Argentina Australia1 Austria Bahrain Belgium Brazil1 Bulgaria Canada Chile China1 Colombia Croatia CTR211,2 Cyprus Czech Republic Denmark Ecuador Egypt1 El Salvador Finland France Germany OHS 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT 0 1 0 or 1 0 0 or 1 0 1 0 0 0 0 1 0 or 1 1 1 0 or 1 0 0 0 0 or 1 0 or 1 0 or 1 5Ch DCT[1:0] 10 01 11 10 11 01 11 10 10 01 10 11 11 11 11 11 10 01 10 11 11 11 RZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62h LIM[1:0] VOL[1:0] 00 00 00 11 00 11 00 11 00 00 00 00 11 11 11 11 11 00 00 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: 1. See "DC Termination Considerations" on page 24 for more information. 2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 3. Supported for loop current 20 mA. 20 Rev. 2.01
Si3038
Table 19. Country Specific Register Settings (Continued)
Register Country Greece Guam Hong Kong Hungary Iceland India Indonesia Ireland Israel Italy Japan1 Jordan1 Kazakhstan1 Kuwait Latvia Lebanon Luxembourg Macao Malaysia1,3 Malta Mexico Morocco Netherlands New Zealand Nigeria Norway Oman1 Pakistan1 Peru Philippines1 Poland Portugal Romania Russia1 Saudi Arabia Singapore OHS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT 0 or 1 0 0 0 0 or 1 0 0 0 or 1 0 or 1 0 or 1 0 0 0 0 0 or 1 0 or 1 0 or 1 0 0 0 or 1 0 0 or 1 0 or 1 1 0 or 1 0 or 1 0 0 0 0 0 0 or 1 0 0 0 0 5Ch DCT[1:0] 11 10 10 10 11 10 10 11 11 11 01 01 01 10 11 11 11 10 01 11 10 11 11 10 11 11 01 01 10 01 10 11 10 01 10 10 RZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 RT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 62h LIM[1:0] VOL[1:0] 11 00 00 00 00 00 00 00 11 00 00 00 00 00 11 00 11 00 11 00 00 00 00 00 00 11 11 11 00 00 11 00 11 11 00 11 11 00 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: 1. See "DC Termination Considerations" on page 24 for more information. 2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 3. Supported for loop current 20 mA.
Rev. 2.01
21
Si3038
Table 19. Country Specific Register Settings (Continued)
Register Country Slovakia Slovenia South Africa South Korea Spain Sweden Switzerland Syria1 Taiwan1 Thailand1 UAE United Kingdom USA Yemen OHS 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ACT 0 0 0 0 0 or 1 0 or 1 0 or 1 0 0 0 0 0 or 1 0 0 5Ch DCT[1:0] 10 10 10 10 11 11 11 01 01 01 10 11 10 10 RZ 0 1 1 0 0 0 0 0 0 0 0 0 0 0 RT 0 1 0 0 0 0 0 0 0 0 0 0 0 0 62h LIM[1:0] VOL[1:0] 00 00 00 00 00 00 00 11 11 11 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: 1. See "DC Termination Considerations" on page 24 for more information. 2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 3. Supported for loop current 20 mA.
Initialization
When the Si3038 is initially powered up, the RESET pin should be asserted. When the RESET pin is deasserted, the registers will have default values. This reset condition guarantees the line-side chip (Si3014) is powered down with no possibility of loading the line (i.e., off-hook). An example initialization procedure is outlined below:
1. Execute a register reset by writing (any value) to register 3Ch. 2. Program the desired sample rate with register 40h (42h). See register 40h (42h) description on page 41 for allowable sample rates. 3. Write 0x0000 to register 3Eh to power up the Si3038. 4. Wait for the Si3038 to complete power up. The lower 8 bits indicate that the Si3038 is ready. If the Si3038 is configured as line #1 codec, 3Eh[7:0] = 0x0F indicates readiness. If the codec is configured as line #2, 3Eh[7:0] = 0x33 indicates readiness. 5. Program GPIO registers to desired modes (registers 4Ch- 54h). 6. Program DAC/ADC levels with register 46h (48h). 7. Program desired line interface parameters (i.e., DCT[1:0], ACT, OHS, RT LIM[1:0], and Vol[1:0] as defined in Table 19, "Country Specific Register Settings," on page 20.)
After this procedure is complete, the Si3038 is ready for ring detection and off-hook operation.
AC-Link
AC-link is a bidirectional, fixed rate, serial PCM digital stream. It handles multiple input and output audio streams and control register accesses employing a time-division multiplexing (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. The AC-link serial interconnect defines a digital data and control pipe between the controller and the codec. The AC-link supports 12 20-bit slots at 48 kHz on SDATA_IN and SDATA_OUT. The TDM "slot-based" architecture supports a per-slot valid tag infrastructure that is the source of each slot's data sets or clears to indicate the validity of the slot data within the current frame. For modem AFE, data streams at a variety of required sample rates can be supported.
Isolation Barrier
The Si3038 achieves an isolation barrier through lowcost, high-voltage capacitors in conjunction with Silicon Laboratories' patented ISOcap signal processing techniques. These techniques eliminate any signal degradation due to capacitor mismatches, common
22
Rev. 2.01
Si3038
mode interference, or noise coupling. As shown in Figure 19 on page 16, the C1, C2, C4, C24, and C25 capacitors isolate the Si3024 (system-side) from the Si3014 (line-side). All transmit, receive, control, ring detect, and caller ID data are communicated through this barrier. Y2 class capacitors may be used for the isolation barrier to achieve surge performance of 5 kV or greater. The ISOcap communications link is disabled by default. The PR bits in register 3Eh must be cleared, and the sample rate must be set in register 40h/42h. No communication between the Si3024 and Si3014 can occur until these conditions are set.
.
Voltage Across DAA ( V )
10.5 10 9.5 9 8.5 8 7.5 7
Japan DCT Mode
Off-Hook
The communication system generates an off-hook command by writing a logic 1 to bit 0 (line 1) or bit 10 (line 2) of slot 12. The off-hook state is used to seize the line for an incoming/outgoing call and can also be used for pulse dialing. When in the on-hook state, negligible dc current flows through the hookswitch. In the off-hook state, the hookswitch transistor pair, Q1 and Q2, turn on. The net effect of the off-hook signal is the application of a termination impedance across TIP and RING and the flow of dc loop current. The termination impedance has both an ac and dc component. When executing an off-hook sequence, the Si3038 requires 1548/Fs seconds to complete the off-hook and provide phone line data on the ac link. This includes the 12/Fs filter group delay. If necessary, for the shortest delay, a higher Fs may be established prior to executing the off-hook. The delay allows line transients to settle prior to normal use.
6.5 6 5.5 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 Loop Current (A)
Figure 21. Japan Mode I/V Characteristics
FCC Mode (DCT[1:0] = 10 b), shown in Figure 22, is the default dc termination mode and supports a transmit full scale level of -1 dBm at TIP and RING. This mode meets FCC requirements in addition to the requirements of many other countries.
12 Voltage Across DAA ( V ) 11 10 9 8 7 6 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 Loop Current (A) FCC DCT Mode
DC Termination
The Si3038 has three programmable dc termination modes, selected with the DCT[1:0] bits in register 5Ch. Japan Mode (DCT[1:0] = 01 b), shown in Figure 21, is a lower voltage mode and supports a transmit full scale level of -2.71 dBm. Higher transmit levels for DTMF dialing are also supported. See "DTMF Dialing" on page 26. The low voltage requirement is dictated by countries such as Japan and Malaysia. Australia has separate dc termination requirements for line seizure versus line hold. The designer can use Japan mode to satisfy both requirements. However, if it is desirable to have a higher transmit level for modem operation, the designer can switch to FCC mode 500 ms after the initial off-hook. This will also satisfy the Australian dc termination requirements.
Figure 22. FCC Mode I/V Characteristics
CTR21 Mode (DCT[1:0] = 11 b), shown in Figure 23, provides current limiting, while maintaining a transmit full scale level of -1 dBm at TIP and RING. In this mode, the dc termination will current limit before reaching 60 mA.
Rev. 2.01
23
Si3038
AC Termination
45 Voltage Across DAA ( V ) 40 35 30 25 20 15 10 5
.015 .02 .025 .03 .035 .04 .045 .05 .055 .06
CTR21 DCT Mode
The Si3038 has two ac termination impedances, selected with the ACT bit in register 5Ch. ACT=0 is a real, nominal 600 termination which satisfies the impedance requirements of FCC part 68, JATE, and other countries. This real impedance is set by circuitry internal to the Si3038 as well as the resistor R2 connected to the REXT pin. ACT=1 is a complex impedance which satisfies the impedance requirements of Australia, New Zealand, South Africa, CTR21, and some European NET4 countries such as the UK and Germany. This complex impedance is set by circuitry internal to the Si3038 as well as the complex network formed by R12, R13, and C14 connected to the REXT2 pin.
Loop Current (A)
Figure 23. CTR21 Mode I/V Characteristics
Ring Detection
The ring signal is capacitively coupled from TIP and RING to the RNG1 and RNG2 pins. The Si3038 supports either full- or half-wave ring detection. With full-wave ring detection, the designer can detect a polarity reversal as well as the ring signal. See "Caller ID" on page 28. The ring detection threshold is programmable with the RT bit in register 5Ch. The ring detector output can be monitored in one of three ways. The first method uses the GPIO1(GPIO11) bit of Slot12. The second method uses the register bits RDTP and RDTN in register 5Eh. The final method uses the SDATA_IN output. The AC'97 controller must detect the frequency of the ring signal in order to distinguish a ring from pulse dialing by telephone equipment connected in parallel. The ring detector mode is controlled by the RFWE bit of register 5Ch. When the RFWE is 0 (default mode), the ring detector operates in half-wave rectifier mode. In this mode, only positive ringing signals are detected. A positive ringing signal is defined as a voltage greater than the ring threshold across RNG1-RNG2. RNG1 and RNG2 are pins 5 and 6 of the Si3014. Conversely, a negative ringing signal is defined as a voltage less than the negative ring threshold across RNG1-RNG2. When the RFWE is 1, the ring detector operates in fullwave rectifier mode. In this mode, both positive and negative ring signals are detected. When RFWE is 0, the GPIO1(GPIO11) bit will be set for a period of time. The GPIO1(GPIO11) bit will not be set for a negative ringing signal. The GPIO1(GPIO11) bit will act as a one shot. Whenever a new ring signal is detected, the one shot is reset. If no new ring signals are detected prior to the one shot counter counting down to zero, then the GPIO1(GPIO11) bit will return to
DC Termination Considerations
Under certain line conditions, it may be beneficial to use other dc termination modes not intended for a particular world region. For instance, in countries that comply with the CTR21 standard, improved distortion characteristics can be seen for very low loop current lines by switching to FCC mode. Thus, after going off-hook in CTR21 mode, the loop current monitor bits (LCS[3:0]) may be used to measure the loop current, and if LCS[3:0] < 3, it is recommended that FCC mode be used. Additionally, for very low voltage countries, such as Japan and Malaysia, the following procedure may be used to optimize distortion characteristics and maximize transmit levels:
1. When first going off-hook, use the Japan mode with the VOL bits (Register 62h, bits 6:5) set to 01. 2. Measure the loop current using the LCS[3:0] bits. 3. If LCS[3:0] 2, maintain the current settings and proceed with normal operation. 4. If LCS[3:0] 3, switch to FCC mode, set the VOL bit to 0, and proceed with normal operation. Note: A single decision of dc termination mode following offhook is appropriate for most applications. However, during PTT testing, a false dc termination I/V curve may be generated if the dc I/V curve is determined following a single off-hook event.
Finally, Australia has separate dc termination requirements for line seizure versus line hold. Japan mode may be used to satisfy both requirements. However, if a higher transmit level for modem operation is desired, switch to FCC mode 500 ms after the initial off-hook. This will satisfy the Australian dc termination requirements.
24
Rev. 2.01
Si3038
zero. The length of this count (in seconds) is 65536 divided by the sample rate. The GPIO1(GPIO11) bit will also be reset to zero by an off-hook event. When RFWE is 1, the GPIO1(GPIO11) bit will toggle active low when the ring signal is positive or negative. This makes the ring signal appear to be twice the frequency of the ringing waveform. The RDTP and RDTN behavior is based on the RNG1RNG2 voltage. Whenever the signal RNG1-RNG2 is above the positive ring threshold the RDTP bit is set. Whenever the signal RNG1-RNG2 is below the negative ring threshold the RDTN bit is set. When the signal RNG1-RNG2 is between these thresholds, neither bit is set. If the ISOcap is active and the device is not off-hook or not in on-hook line monitor mode, the ring data will be presented on SDATA_IN. The waveform on SDATA_IN depends on the state of the RFWE bit. When RFWE is 0, SDATA_IN will be -32768 (8000h) while the RNG1-RNG2 voltage is between the thresholds. When a ring is detected, SDATA_IN will transition rather quickly to +32767 while the ring signal is positive, then go back to -32768 while the ring is near zero and negative. Thus a near square wave is presented on SDATA_IN that swings from -32768 to +32767 in cadence with the ring signal. When RFWE is 1, SDATA_IN will sit at approximately +1228 while the RNG1-RNG2 voltage is between the thresholds. When the ring goes positive, SDATA_IN will transition to +32767. When the ring signal goes near zero, SDATA_IN will remain near 1228. Then as the ring goes negative, the SDATA_IN will transition to -32768. This will repeat in cadence with the ring signal. The best way to observe the ring signal on SDATA_IN is simply to observe the MSB of the data. The MSB will toggle in cadence with the ring signal independent of the ring detector mode. This is adequate information for determining the ring frequency. The MSB of SDATA_IN will toggle at the same frequency as the ring signal. setting the RZ bit in register 5Ch.
Wake-Up on Ring
Ring is an example of an event that might need to wakeup a PC that has suspended into a low-power state. Power management, or wake, event support for a modem is a key feature of the current PC industry standards. The Si3038 provides wake-up on ring through the AClink as defined by the AC'97 ver 2.1 specification. In an implementation designed for wake-on ring, where the Si3038 and AC-link are both completely powered by Vaux, a ring detected at the RNG1 and RNG2 pins of the Si3038 causes the assertion of the power management signal to the system. The power management signal is the rising edge of the SDATA_IN signal when the Si3038 is in low-power mode. The power management event signal assertion causes the system to resume so that the modem event (ring) can be serviced. The first thing that the device driver must do to reestablish communications with the Si3038 is to command the AC'97 Digital Controller to execute a warm reset to the AC-link. Figure 24 illustrates the entire sequence. The rising edge of SDATA_IN causes the AC'97 Digital Controller to assert its power management signal to the system's ACPI controller. The Si3038 will keep SDATA_IN high until it has sampled SYNC having gone high, and then Low (warm reset). The power management event is cleared out in the AC'97 Digital Controller by system software, asynchronous to AC-link activity. The AC'97 Digital Controller should always monitor the Si3038's ready bit before sending data to it. The modem driver should read the GPIO Pin Status register to determine if the wake event was due to the ring signal before executing a register reset. Before entering the low-power mode, the Si3038 must be enabled to cause the wake signal when receiving a ring. This is done by programming the GPIO Pin Sticky (50h) and GPIO Wake Up Mask (52h) registers and clearing previous sticky GPIO events. Before setting the MLNK bit the driver should do the following:
1. Set the GS1 bit in register 50h (GS11 if using line #2) 2. Set the GW1 bit in register 52h (GW11 for line #2) 3. Clear a possible old sticky event by writing a 0 to the GI1 (GI11 for line #2) bit in read only register GPIO Pin Status register (54h).
Ringer Impedance
The ring detector in many DAAs is ac coupled to the line with a large, 1 uF, 250 V decoupling capacitor. The ring detector on the Si3038 is also capacitively coupled to the line, but it is designed to use smaller, less expensive capacitors (C7, C8). Inherently, this network produces a high ringer impedance to the line of approximately 800 to 900 k. This value meets the majority of country PTT specifications, including FCC and CTR21. Several countries including Poland, South Africa and Slovenia, require a maximum ringer impedance that can be met with an internally synthesized impedance by
If the AC'97 Digital Controller allows the RESET signal to go low during the low-power mode of the Si3038. The wake event will be a cold reset (rising edge of RESET) and the modem driver should re-program the GPIO Pin Sticky register to set the GS1 (or GS11) bit. This will allow the modem driver to read the sticky value of the
25
Rev. 2.01
Si3038
GPIO Pin Status register. The Si3038 can also be programmed to wake up on events due to GPIO_A and GPIO_B. the OHS bit in register 5Ch can be used to slowly ramp down the loop current to pass these tests without requiring additional components.
DTMF Dialing
In CTR21 dc termination mode, the DIAL bit in register 62h should be set during DTMF dialing if the LCS[3:0] bits are less than 6. Setting this bit increases headroom for large signals. This bit should not be used during normal operation or if LCS[3:0] greater than 5. In Japan dc termination mode the Si3038 attenuates the transmit output by 1.7 dB to meet headroom requirements. This attenuation can be removed when DTMF dialing is desired in this mode. When in the FCC dc termination mode, the FJM bit in register 62h will enable the Japan dc termination mode without the 1.7 dB attenuation. Increased distortion may be observed, which is acceptable during DTMF dialing. After DTMF dialing is complete, the attenuation should be enabled by setting the Japan dc termination mode DCT[1:0]=01b. The FJM bit has no effect in Japan dc termination mode. Higher DTMF levels may also be achieved if the amplitude is increased and the peaks of the DTMF signal are clipped at digital full scale (as opposed to wrapping). Clipping the signal will produce some distortion and intermodulation of the signal. Generally, somewhat increased distortion (up to 10%) is acceptable during DTMF signaling. Several dB higher DTMF levels can be achieved with this technique, compared with a digital full scale peak signal.
Billing Tone Detection
"Billing tones" or "Metering Pulses" generated by the central office can cause modem connection difficulties. The billing tone is typically either a 12 KHz or 16 KHz signal and is sometimes used in Germany, Switzerland, and South Africa. Depending on line conditions, the billing tone may be large enough to cause major errors related to the modem data. The Si3038 chipset has a feature which allows the device to remain off-hook during billing tones and provide feedback as to whether a billing tone has occurred and when it ends. Billing tone detection is enabled by setting the BTE bit (register 5Ch). Billing tones less than 1.1 VPK on the line will be filtered out by the low pass digital filter on the Si3038. The ROV bit is set when a line signal is greater than 1.1 VPK, indicating an ADC overload condition. The BTD bit is set when a line signal (billing tone) is large enough to excessively reduce the internal power supply of the line-side device (Si3014). When the BTD bit is set, the dc termination is released to maintain an off hook condition, and the line is presented with an 800 dc impedance. The OVL bit should be monitored (polled) following a billing tone detection. When the OVL bit returns to zero, indicating that the billing tone has passed, the BTE bit should be written to zero to return the dc termination to its original state. It will take approximately one second to return to normal dc operating conditions. The BTD and ROV bits are sticky, and they must be written to zero to be reset. After the BTE, ROV, and BTD bits are all cleared, the BTE bit can be set to reenable billing tone detection. Certain line events, such as an off-hook event on a parallel phone or a polarity reversal, may trigger the ROV or the BTD bits, after which the billing tone detector must be reset. The user should look for multiple events before qualifying whether billing tones are actually present.
Pulse Dialing
Pulse dialing is accomplished by going off- and on-hook to generate make and break pulses. The nominal rate is 10 pulses per second. Some countries have very tight specifications for pulse fidelity, including make and break times, make resistance, and rise and fall times. In a traditional solid-state dc holding circuit, there are a number of issues in meeting these requirements. The Si3038 dc holding circuit has active control of the on-hook and off-hook transients to maintain pulse dialing fidelity. Spark quenching requirements in countries such as Italy, the Netherlands, South Africa, and Australia deal with the on-hook transition during pulse dialing. These tests provide an inductive dc feed, resulting in a large voltage spike. This spike is caused by the line inductance and the sudden decrease in current through the loop when going on-hook. The traditional way of dealing with this problem is to put a parallel RC shunt across the hookswitch relay. The capacitor is large (~1 uF, 250 V) and relatively expensive. In the Si3038,
26
Rev. 2.01
Si3038
Power Down Fram e SYNC BIT_CLK SDATA_OUT SDATA_IN
slot 12 prev. frame
Sleep State
W ake Event
New Audio Fram e
TAG
W rite to 56th
Data MLNK
TAG
Slot 1
Slot 2
s lot 12 prev. fram e
TAG
TAG
Slot 1
Slot 2
Figure 24. AC-Link Power-Down/Up Sequence
Although the DAA will remain off-hook during a billing tone event, the received data from the line will be corrupted when a billing tone occurs. If the user wishes to receive data through a billing tone, an external LC filter must be added. A modem manufacturer can provide this filter to users in the form of a dongle that connects on the phone line before the DAA. This keeps the manufacturer from having to include a costly LC filter internal to the modem when it may only be necessary to support a few countries. Alternatively, when a billing tone is detected, the system software may notify the user that a billing tone has occurred. This notification can be used to prompt the user to contact the telephone company and have the billing tones disabled or to purchase an external LC filter.
C1
C2 L1 TIP
From Line
L2 C3
To DAA
Billing Tone Filter (Optional)
In order to operate without degradation during billing tones in Germany, Switzerland, and South Africa, an external LC notch filter is required. (The Si3038 can remain off-hook during a billing tone event, but modem data will be lost in the presence of large billing tone signals.) The notch filter design requires two notches, one at 12 KHz and one at 16 KHz. Because these components are fairly expensive and few countries supply billing tone support, this filter is typically placed in an external dongle or added as a population option for these countries. Figure 25 shows an example billing tone filter. L1 must carry the entire loop current. The series resistance of the inductors is important to achieve a narrow and deep notch. This design has more than 25 dB of attenuation at both 12 KHz and 16 KHz.
RING
Figure 25. Billing Tone Filter
`
Table 20. Component Values--Optional Billing Tone Filters
Symbol C1,C2 C3 L1 L2 Value 0.027 F, 50 V, 10% 0.01 F, 250 V, 10% 3.3 mH, >120 mA, <10 , 10% 10 mH, >40 mA, <10 , 10%
The billing tone filter effects the ac termination and return loss. The current complex ac termination will pass worldwide return loss specifications both with and without the billing tone filter by at least 3 dB. The ac termination is optimized for frequency response and hybrid cancellation, while having greater than 4 dB of margin with or without the dongle for South Africa, Australia, CTR21, and German and Swiss countryspecific specifications.
Rev. 2.01
27
Si3038
On-Hook Line Monitor
The Si3038 allows the user to receive line activity when in an on-hook state. The LINE1_CID/LINE2_CID bit in slot 12 enables a low-power ADC which digitizes the signal passed across the RNG1/2 pins. This signal is passed across the ISOcap to the AC'97 controller. A current of approximately 450 A is drawn from the line when this bit is activated. This mode is typically used to detect caller ID data (see the "Caller ID" section). The on-hook line monitor can also be used to detect whether a phone line is physically connected to the Si3014 and associated circuitry. If a line is present and the LINE1_CID/LINE2_CID bit is set, SDATA_IN will have a near zero value and the LCS[3:0] bits will read 1111b. Due to the nature of the low-power ADC, the data presented on SDATA_IN could have up to a 10% dc Offset. If no line is connected, the output of SDATA_IN will move towards a negative full scale value (-32768). The value is guaranteed to be at least 89% of negative full scale. In addition, the LCS[3:0] bits will be zero. therefore, if a battery reversal occurs, the AC'97 controller should wait a minimum of 40 ms to verify that the event observed is a battery reversal and not a ring signal. This time is greater than half the period of the longest ring signal. If another edge is detected during this 40 ms pause, this event is characterized as a ring signal and not a battery reversal. If it is a battery reversal, the AC'97 controller should set the SQLH bit for a period of at least 1 ms. This resets the ac coupling network on the ring input in preparation for the caller ID data. The SQLH bit is then cleared, and the LINE1_CID/ LINE2_CID should be asserted to enable the caller ID data to be passed to the AC'97 controller and presented on SDATA_IN. The bit should be cleared after the AC'97 controller has received the caller ID data. Due to the nature of the low-power ADC, the data presented on SDATA_IN will have up to a 10% dc Offset. The caller ID decoder must either use a high pass or band pass filter to accurately retrieve the caller ID data.
Caller ID
The Si3038 provides the designer with the ability to pass caller ID data from the phone line to the AC-link interface. In countries where the caller ID data is passed on the phone line between the first and second rings, the following method should be utilized to capture the caller ID data. The RDTP and RDTN register bits should be monitored to determine the completion of the first ring. After completion of the first ring, the AC'97 controller should set the SQLH bit (register 5Ch) for a period of at least 1 ms. This resets the ac coupling network on the ring input in preparation for the caller ID data. The SQLH bit is then cleared, and the LINE1_CID/ LINE2_CID (slot 12, GPIO2/12) should be asserted to enable the caller ID data to be passed to the AC'97 controller on SDATA_IN. This bit enables a low-power ADC (approximately 450 A is drawn from the line) which digitizes the signal passed across the RNG1/2 pins. This signal is passed across the ISOcap to the AC'97 controller. The LINE1_CID/LINE2_CID bit should be cleared after the caller ID data is received and prior to the second ring. In systems where the caller ID data is preceded by a line polarity (battery) reversal, the following method should be used to capture the caller ID data. The Si3038 supports both full- and half-wave rectified ring detection. Because a polarity reversal will trip either the RDTP or RDTN ring detection bits, the user must distinguish between a polarity reversal and a ring. This is accomplished using the full-wave ring detector in the device. The lowest specified ring frequency is 15 Hz;
28
Loop Current Monitor
It may be desirable to have a measurement of the loop current being drawn from the line. This measurements can be used to tell whether a telephone line is connected, whether a parallel handset has been picked up, or if excessive loop current is present. When the system is in an off-hook state, the LCS bits of register 5Eh indicate the approximate amount of dc loop current. The LCS is a 4-bit value ranging from zero to fifteen. Each unit represents approximately 6 mA of loop current from LCS codes 1-14. The typical LCS transfer function is shown in Figure 26:
15
10 LCS BIT 5
0 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 96 Loop Current (mA) 155
Figure 26. Typical LCS Transfer Function
An LCS value of zero means the loop current is less than required for normal operation and the system should be on-hook. Typically, an LCS value of 15 means the loop current is greater than 155 mA. The LCS detector has a built-in hysteresis of 2 mA. This allows for a stable LCS value when the loop current is
Rev. 2.01
Si3038
near a transition level. The LCS value is a rough approximation of the loop current, and the designer is advised to use this value in a relative means rather than an absolute value. This feature enables the modem to determine if an additional line has "picked up" while the modem is transferring information. In the case of a second phone going off-hook, the loop current falls approximately 50% and is reflected in the value of the LCS bits. provides a much lower, however non-linear, group delay than the default FIR filters.
In-Circuit Testing
The Si3038's advanced design provides the modem manufacturer with increased ability to determine system functionality during production line tests, as well as user diagnostics. Several loopback modes exist allowing increased coverage of system components. The loopback mode allows the data pump to provide a digital input test pattern on SDATA_IN and receive a corresponding digital test pattern back on SDATA_OUT. To enable this mode, set L1B[2:0](L2B[2:0])=101 in register 56h. In this mode, the isolation barrier is actually being tested. The digital stream is delivered across the isolation capacitors, C1 and C2 of Figure 19 on page 16, to the line-side device and returned across the same barrier. The digital DAC loopback mode allows data to be sent on the digital path from SDATA_IN to the digital section of DAC to ADC to SDATA_OUT. This loopback mode is used when the line-side chip is in power-down mode. To enable this mode, set L1B[2:0](L2B[2:0]) = 011 in register 56h. The remote analog loopback mode allows an external device to drive the receive pins of the line-side chip and receive the signal from the transmit pins. This mode allows testing of external components connecting the RJ-11 jack (TIP and RING) to the line side of the Si3014. To enable this mode, set L1B2:0(L2B2:0) = 100 in register 56h. The ADC loopback mode allows an external device to drive the receive pins of the Si3014. The signal is then digitized on the Si3014 and sent to the Si3024, which sends the data back to the Si3014. The signal is then converted back to analog. The external device receives the signal on the transmit pins. This mode allows testing of the Si3038s converters and external devices between the Si3014 and RJ-11 jack. To enable this mode, set the L1B[2:0](L2B[2:0]) = 001. The final two testing modes, local analog loopback and external analog loopback, allow the system to test the basic operation of the converters on the line side and the functionality of the external components. In local analog loopback mode, the AC'97 controller provides a digital test waveform on SDATA_OUT. This data is passed across the isolation barrier, converted to analog, internally looped to the receive path, converted to digital, passed back across the isolation barrier, and presented to the AC'97 controller. To enable local and analog loopback, set L1B2:0 (L2B2:0) = 010. External analog loopback mode allows the system to test external components by passing converted data (from
29
Overload Detection
The Si3038 can detect if an overload condition is present which may damage the DAA circuit. The DAA may be damaged if excessive line voltage or loop current is sustained. In FCC and Japan dc termination modes, an LCS[3:0] value of 1111b means the loop current is greater than 120 mA indicating the DAA is drawing excessive loop current. In CTR21 mode, 120 mA of loop current is not possible due to the current limit circuit. In this dc termination mode, an LCS[3:0] value of 1000b (8 decimal) or greater indicates an excessive loop current condition.
Analog Output
The Si3038 supports an analog output (AOUT) for driving the call progress speaker. AOUT is an analog signal comprised of a mix of the transmit and receive signals. The AOUT level can be adjusted via the ATM and ARM bits in control register 5Ch. The transmit portion of AOUT can be set to -20 dB, -26 dB, -32 dB, or mute. The receive portion of AOUT can be set to 0 dB, -6 dB, -12 dB, or mute. Figure 20 on page 19 illustrates a recommended application circuit. Note that in the configuration shown, the LM386 provides a gain of 26 dB. Additional gain adjustments may be made by varying the voltage divider created by R1 and R3.
Gain Control
The Si3038 supports multiple gain and attenuation settings in register 46h/48h for the receive and transmit paths, respectively. The receive path can support gains of 0, 3, 6, 9, and 12 dB, as selected by ADC[3:1] bits. The receive path can also be muted by setting bit 7. The transmit path can support attenuations of 0, 3, 6, 9, and 12 dB, as selected by DAC[3:1] bits. The transmit path can also be muted by setting bit 15.
Filter Selection
The Si3038 supports additional filter selections for the receive and transmit signals. The IIRE bit of register 5Ch, when set, enables the IIR filters. This filter
Rev. 2.01
Si3038
SDATA_IN) to the transmit pin, which is looped externally to the receive pin. To enable external analog loopback, set L1B2:0 (L2B2:0) = 110. Both analog loopback modes require power, which is typically supplied by the loop current from TIP and RING.
Clocking
The Si3024 derives its internal clock, when primary, from the 24.576 MHz clock and drives a buffered and divided down (1/2) clock to its digital companion controller over AC-link through the BIT_CLK signal. Clock jitter at the DACs and ADCs is a fundamental impediment to high quality output, and the internally generated clock provides the Si3024 with a clean clock that is independent of the physical proximity of the Si3024's companion AC'97 controller. The beginning of all audio sample packets, or Audio Frames, transferred over AC-link is synchronized to the rising edge of the SYNC signal. SYNC is driven by the AC'97 controller. The AC'97 controller takes BIT_CLK as an input and generates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This yields a 48-kHz SYNC signal whose period defines an audio frame. Data is transitioned on AC-link on each rising edge of BIT_CLK, and subsequently sampled on the receiving side of AC-link on each immediately following falling edge of BIT_CLK.
Digital Interface
The ID pins configure the Si3024 as a primary or secondary AC'97 device as shown in Table 21.
Table 21. Device ID Configuration
ID1 1 1 0 0 ID0 1 0 1 0 Device Primary device Secondary device #1 Secondary device #2 Factory Test
The following sections describe Si3024 operation.
Si3024 as Secondary Device
The Si3024 can operate as a secondary device, which allows up to two Si3024s to exist on the AC link along with a primary device. The primary device can be an AC'97 Rev. 2.1-compatible codec or an Si3024 configured as the primary device. When configured as a secondary device, the Si3024's BIT_CLK becomes an input and is used as the master clock.
Resetting Si3038 Chipset
There are three types of reset: Cold reset--Initializes all Si3038 logic (registers included) to its default state. Initiated by bringing RESET low at least 1 s during a time when BIT_CLK is inactive. Warm reset--Leaves the register contents unaltered. Initiated by bringing SYNC high for at least 1 s in the absence of BIT_CLK. Register reset--Initializes only the registers to their default states. Initiated by a write to register 3Ch. After signaling a reset to the Si3038 chipset, the AC'97 controller should not attempt to play or capture modem data until it has sampled a Codec Ready indication from the Si3038 chipset. See "AC-Link Audio Input Frame (SDATA_IN)" on page 34.
Si3024 as Primary MC'97 Codec
The Si3024 can operate as a primary AC'97 Rev 2.1 compatible codec. However, when there is an audio AC'97 codec present on the AC-link, the Si3024 should be configured as a secondary codec, and the audio AC'97 codec should be configured as the primary. When the Si3024 is configured as a primary device, clocking is derived from a 24.576 MHz crystal across the XIN and XOUT pins. An external 24.576 MHz Master Clock can also be applied to XIN.
Si3024 Connection to the Digital AC'97 controller
The Si3024 communicates with its companion AC'97 controller through a digital serial link called the AC-link. All digital audio streams, optional modem line codec streams, and command/status information is communicated over this point-to-point serial interconnect. Figure 27 illustrates the breakout of the connecting signals.
30
Rev. 2.01
Si3038
SYNC BIT_CLK Digital AC'97 Controller SDATA_OUT SDATA_IN RESET Si3024
Figure 27. Si3038 Connection To AC'97 Controller (Primary Device Configuration)
AC-Link Digital Serial Interface Protocol
The Si3024 incorporates a 5-pin digital serial interface that links it to the AC'97 controller. AC-link is a bidirectional, fixed rate, serial PCM digital stream. It handles multiple input and output audio streams (including modems), as well as control register accesses employing a TDM scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. The Si3024 data streams are as follows: Control--Control register write port; two output slots Status--Control register read port; two input slots Modem Line Codec Output--Modem line codec DAC input stream; one output slot per line Modem Line Codec Input--Modem line codec ADC output stream; one input slot per line
I/O Control--DAA control and GPIO; one output slot I/O Status--DAA status and GPIO; one input slot Synchronization of all AC-link data transactions is signaled by the AC'97 controller. The Si3024 drives the serial bit clock onto AC-link, which the AC'97 controller then qualifies with a synchronization signal to construct audio frames. The SYNC signal, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link data, the Si3024 for outgoing data and the AC'97 controller for incoming data, samples each serial bit on the falling edges of BIT_CLK.
Slot #
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC SDATA_OUT
Tag
CMD ADDR CMD DATA PCM L PCM R Line 1 DAC PCM Center PCM PCM L SURR R SURR PCM LFE Line 2 DAC PCM L (n+1) Status ADDR Status DATA PCM L PCM R Line 1 ADC MIC ADC Line 2 ADC HSET DAC PCM R (n+1) HSET ADC
IO CTRL
PCM C (n+1)
Codec ID SDATA_IN
Tag
RSRVD RSRVD RSRVD
IO STATUS
SLOTREQ 3-12
Figure 28. Standard Bi-Directional Audio Frame
Rev. 2.01
31
Si3038
Tag Phase 20.8 S (48 KHz) Data Phase
SYNC BIT_CLK SDATA_OUT
12.228 MHz 81.4 nS
Valid Frame
slot(1)
slot(2)
slot(12)
"0"
"0"
"0"
19
0
19
0
19
0
19
0
End of previous Audio Frame
Time Slot "Valid" Bits ("1" = Time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
Figure 29. AC-Link Audio Output Frame
The AC-link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream and contains valid data. If a slot is tagged invalid, it is the responsibility of the data source (the Si3024 for the input stream, the AC'97 controller for the output stream) to populate all bit positions with 0s during that slot's active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is called the Tag Phase. The remainder of the audio frame where SYNC is low is called the data phase. See Figure 28. Additionally, for power savings, all clock, sync, and data signals can be halted. The Si3038 chipset maintains its register contents intact when entering a power-savings mode. AC-Link Audio Output Frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the Si3038's DAC inputs and control registers. Each audio output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits used for AC-link protocol infrastructure. Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the Valid Frame bit is a 1, the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by the Si3024 indicate which of the corresponding 12 time slots contain valid data. In this way, data streams of differing sample rates can be transmitted across AC-link at its fixed 48-kHz audio frame rate. Figure 29 illustrates the time slotbased AC-link protocol. A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising
32
edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the Si3024 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC'97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the Si3024 on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. See Figure 30.
AC '97 samples SNYC assertion here
SYNC BIT_CLK SDATA_OUT
AC '97 samples SDATA_O UT bit of frame here
Valid Frame
slot (1) slot (2)
End of previous Audio Frame
Figure 30. Start of an Audio Output Frame
SDATA_OUT's composite stream is MSB justified (MSB first) with all non-valid slots' bit positions padded with 0s by the AC'97 controller. In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC'97 controller always pads all trailing non-valid bit positions of the 20bit slot with 0s. Variable Sample Rate Signaling Protocol For variable sample rate output, the codec examines its sample rate control registers, the state of its FIFOs, and
Rev. 2.01
Si3038
the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits (bit 4 or 9 in SDATA_IN Slot 1) to set active (low). SLOTREQ bits asserted during the current audio input frame signal which active output slots require data from the AC'97 Digital Controller in the next audio output frame. An active output slot is defined as any slot supported by the codec that is not in a power-down state. The SLOTREQ signal is dependent on the current power state. The following is a list of conditions in which the SLOTREQ for slot 5 is active and conditions in which it is inhibited: SLOTREQ is active every frame when the PRD/PRF is set (Reg 3E, bit 11/13). (DAC is powered down.) This is required by the AC'97 specification for compatibility with 48 kHz AC'97 rev. 1.03 codecs. SLOTREQ is inhibited (high) if the MLNK bit is set (register 56, bit 12), and AC-Link halt is impending. Slot 1: Command Address Port The Command Address Port controls features and monitors status (see Audio Input Frame Slots 1 and 2) for Si3038 chipset functions including, but not limited to, sample rate, AFE configuration, and power management. The control interface architecture supports up to 64 16-bit read/write registers addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid; odd register (01h, 03h, etc.) writes are ignored and reads return 0. Note that shadowing of the control register file on the AC'97 controller is an option left open to the implementation of the AC'97 controller. The Si3038's control register file is readable as well as writable to provide more robust testability. Audio output frame slot 1 communicates control register address and write/read command information to the Si3038 chipset. Command Address Port bit assignments: Bit(19)--Read/Write command (1=read, 0=write) Bit(18:12)--Control Register Index (64 16-bit locations, addressed on even byte boundaries) Bit(11:0)--Reserved (padded with 0s) The first bit (MSB) sampled by the Si3024 indicates whether the current control transaction is a read or a write operation. The following seven bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must be padded with 0s by the AC'97 controller. Slot 2: Command Data Port The Command Data Port delivers 16-bit control register write data in the event that the current command port
Rev. 2.01 33
operation is a write cycle as indicated by Slot 1, bit 19. Command Data Port bit assignments: Bit(19:4)--Control Register Write Data (padded with 0s if the current operation is a read) Bit(3:0)--Reserved (padded with 0s) Slot 5: Modem Line 1 DAC Audio output frame slot 5 contains MSB-justified modem DAC output data for phone line #1 (ID = 0 or 1). The modem DAC output resolution is 16 bits. The Si3038 receives its DAC data MSB first. Slot 5 data is sent by the controller at a rate below the 48 kHz rate of the AC-Link. Therefore, "tags" are used to mark when there is valid data in slot 5. The tag for slot 5 is bit 10 in slot 0. Tag bits are sent by the controller in response to a SLOTREQ on SDATA_IN. Slot 10: Modem Line 2 DAC Line 2 is assigned to slot 10. The leading 16-bits of each slot must contain valid sample data (MSB bit 19, LSB 4).
Si3038
Table 22. Slot 12
GPIO
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9:6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Vendor Optional Bit 3 Bit 2 Bit 1 Bit 0 Reserved LINE2_FDT LINE1_FDT GPIO_INT in in in Frame Detect, Line 2 Frame Detect, Line 1 GPIO state change
Name
LINE2_GPIO_B LINE2_GPIO_A LINE2_DLCS LINE2_CID LINE2_RI LINE2_OH Reserved LINE1_GPIO_B LINE1_GPIO_A LINE1_DLCS LINE1_CID LINE1_RI LINE1_OH
Sense
in/out in/out in out in out
Description
GPIO pin B, Line 2 GPIO pin A, Line 2 Delta Loop Current Sense, Line 2 Caller ID path enable, Line 2 Ring Detect, Line 2 Off Hook, Line 2
in/out in/out in out in out
GPIO pin B, Line 1 GPIO pin A, Line 1 Delta Loop Current Sense, Line 1 Caller ID path enable, Line 1 Ring Detect, Line 1 Off Hook, Line 1
Slot 12: Modem GPIO Control Slot 12 contains latency critical signals for the Si3014 and the GPIO of the Si3024. See Table 22. Slots 3, 4, 6-9, 11: Not Used The Si3038 always pads audio output frame slots 3, 4, 6-9, and 11 with 0s. AC-Link Audio Input Frame (SDATA_IN) The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC'97 controller. This is the case with the audio output frame; each AC-link audio input frame consists of 12 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits that are used by the AC-link protocol infrastructure. Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) that flags whether the Si3024 is in the Codec Ready state or not. If the Codec Ready bit is a 0, the Si3024 is not ready for normal operation. This condition is normal following the deassertion of reset (e.g., while the Si3024's voltage references settle). When the AClink Codec Ready indicator bit is a 1, the AC-link and
34
Si3024 control and status registers are in a fully operational state. The AC'97 controller must further probe the Powerdown Control/Status register to determine exactly which subsections, if any, are ready. Before any attempts to put the Si3038 chipset into operation, the AC'97 controller should poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that the Si3024 is Codec Ready. When the Si3024 is sampled Codec Ready, then the next 12 bit positions sampled by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. Figure 31 illustrates the time slot-based AC-link protocol. A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the next falling edge of BIT_CLK, the Si3024 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the Si3024 transitions SDATA_IN into the first bit position of slot 0 (Codec
Rev. 2.01
Si3038
Ready bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and unassigned time slots) padded with 0s by the Si3024. SDATA_IN data is sampled on the falling edges of BIT_CLK by the AC'97 controller. Slot 1: Status Address Port The Status Address Port monitors status for Si3024 functions including, but not limited to, line-side configuration. Audio input frame slot 1's stream echoes the control register index for historical reference and for the data to be returned in slot 2. (Assuming that slots 1 and 2 have been tagged "valid" by the Si3024 during slot 0). Status Address Port bit assignments: Bit(19)--Reserved (padded with 0) Bit(18:12)--Control Register Index (Echo of register index for which data is being returned) Bit(11:2)--SLOTREQ bits, bit 9 for Line 1 and bit 4 for Line 2. (See "Variable Sample Rate Signaling Protocol" on page 32 for more details.) Bit(1,0)--Reserved (padded with 0s) The first bit (MSB) generated by the Si3024 is always padded with a 0. The following seven bit positions communicate the associated control register address and the trailing 12 bit positions are padded with 0s by the Si3024. Slot 2: Status Data Port The Status Data Port delivers 16-bit control register read data. Status Data Port bit assignments: Bit(19:4)--Control Register Read Data (padded with 0s if tagged invalid by the Si3024) Bit(3:0)--Reserved (padded with 0s) If Slot 2 is tagged invalid by the Si3024, then the entire slot is padded with 0s by the Si3024. Slot 5: Modem Line 1 ADC Audio input frame slot 5 contains MSB-justified modem ADC output data for phone line #1 (ID = 0 or 1). The modem ADC output resolution is 16 bits. The Si3038 ships out its ADC output data MSB first and pads any trailing non-valid bit positions with 0s to fill out its 20-bit time slot. Slot 5 data is sent by the controller at a rate below the 48 kHz rate of the AC-Link. Therefore, "tags" are used to mark when there is valid data in slot 5. The tag for slot 5 is bit 10 in slot 0. The tag for slot 5 (and slot 10) is dependent on the current power state. Slot 5 is inhibited by the following: PRC/PRE bit is set (register 3E, bit 10/12); ADC is powered down. MLNK bit is set (register 56, bit 12); AC-Link halt is impending. Note that slot 5 is active when the DAA is on-hook in order to pass ringer and caller-ID data. Slot 10: Modem Line 2 ADC Audio input frame for Line 2. Slot 12: Modem GPIO Status Slot 12 contains latency critical signals for the Si3014 and the GPIO of the Si3024. Slot 12 also reflects the status of the link between the Si3024 and Si3014. See Table 22.
Tag Phase
20.8 S (48 KHz)
Data Phase
SYNC BIT_CLK SDATA_IN
12.228 MHz 81.4 nS
Codec Ready
slot(1)
slot(2)
slot(12)
"0"
"0"
"0"
19
0
19
0
19
0
19
0
End of previous Audio Frame
Time Slot "Valid" Bits ("1" = Time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
Figure 31. AC-Link Audio Input Frame
Rev. 2.01
35
Si3038
Codec Register Access
Whenever the AC'97 Digital Controller addresses the Si3024 as a primary codec or the codec responds to a read command, Slot 0 Tag bits should always be set to indicate actual valid data in Slot 1 and Slot 2. See Table 23. When the AC'97 Digital Controller addresses the Si3024 as a secondary codec, the Slot 0 Tag bits for Address and Data must be zero. A non-zero, 2-bit codec ID in the LSBs of Slot 0 indicates a valid Read or Write Address in Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2. See Table 24. In order for the AC'97 Digital Controller to independently access Primary and Secondary Codec registers, a 2-bit Codec ID field (chip select) is used in the LSBs of Output Slot 0. For Secondary Codec access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01 or 10) into the Codec ID field (Slot 0, bits 1 and 0). When configured as a secondary codec, the Si3024 disregards the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits when a 2-bit Codec ID value (Slot 0, bits 1 and 0) is sent that matches the ID configuration. In a sense, the Secondary Codec ID field functions as an alternative Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator. The Si3024 monitors the Frame Valid bit and ignores the frame (regardless of the state of the Secondary Codec ID bits) if it is not valid. The AC'97 Digital Controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the Secondary Codec ID bits are set. See Table 25.
Table 23. Primary Codec Addressing: Slot 0 Tag Bits
Function AC'97 Digital Controller Primary Read Frame N, SDATA_OUT AC'97 Digital Controller Primary Write Frame N, SDATA_OUT Si3024 Status Frame N + 1, SDATA_IN Slot 0, bit 15 (Valid Frame) 1 1 1 Slot 0, bit 14 (Valid Slot 1 Address) 1 1 1 Slot 0, bit 13 (Valid Slot 2 Data) 0 1 1 Slot 0, Bits 1-0 (Codec ID) 00 00 00
Table 24. Secondary Codec Addressing: Slot 0 Tag Bits
Function AC'97 Digital Controller Secondary Read Frame N, SDATA_OUT AC'97 Digital Controller Secondary Write Frame N, SDATA_OUT Si3024 Status Frame N + 1, SDATA_IN Slot 0, bit 15 (Valid Frame) 1 Slot 0, bit 14 (Valid Slot 1 Address) 0 Slot 0, bit 13 (Valid Slot 2 Data) 0 Slot 0, Bits 1-0 (Codec ID) 01 or 10
1
0
0
01 or 10
1
1
1
00
36
Rev. 2.01
Si3038
Table 25. Secondary Codec Register Access Slot 0 Bit Definitions
Bit 15 14 13 12-3 2 1-0 Output Tag Slot (16-bits) Description Frame Valid Slot 1: Valid Command Address bit (Primary Codec only) Slot 2: Valid Command Data bit (Primary Codec only) Slot 3: 12 Valid bits as defined by AC'97 Reserved (Set to 0) 2-bit Codec ID field (00 reserved for Primary; 01, 10 indicate Secondary) reset. The current power down state ultimately dictates which form of reset is appropriate. Unless a cold or register reset (a write to the Reset register) is performed, wherein the registers are initialized to their default values, registers are required to keep state during all power-down modes. When powered down, reactivation of the AC-link through reassertion of the SYNC signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. When AC-link powers up, the Si3038 indicates readiness through the Codec Ready bit (input slot 0, bit 15). The Si3038 can be enabled to indicate a power management event has occurred (e.g., ring detection) while in low-power mode. See "52h GPIO Pin Wake Up Mask" on page 44 for more details. Si3038 Cold Reset A cold reset is achieved by asserting RESET for the minimum specified time. By driving RESET low, BIT_CLK and SDATA_OUT are activated, or reactivated as the case may be, and all Si3038 control registers are initialized to their default power on reset values. It should be noted that while RESET is low, the Si3038 will remain active. Upon the rising edge of RESET the Si3038 will perform a cold reset. RESET is an asynchronous Si3038 input. Si3038 Warm Reset A warm reset reactivates the AC-link without altering the current Si3038 register values. A warm reset is signaled by driving SYNC high for a minimum of 1 s in the absence of BIT_CLK. Within normal audio frames, SYNC is a synchronous Si3038 input. However, in the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a Warm reset to the Si3038. The primary AC'97 codec will NOT respond with the activation of BIT_CLK until SYNC has been sampled low again by AC'97. This will preclude the false detection of a new audio frame.
37
AC-Link Low Power Mode
The AC-link signals can be placed in a low-power mode. When AC'97's Powerdown Register is programmed to the appropriate value, both BIT_CLK and SDATA_IN will be brought to, and held, at a logic low voltage level.
SYNC BIT_CLK SDATA_OUT SDATA_IN
slot 12 prev. frame TAG Write to 56h Data MLNK
slot 12 prev. frame
TAG
Figure 32. AC-Link Powerdown Timing
BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to the register 56h with MLNK. When the AC'97 controller driver is at the point where it is ready to program the AC-link into its low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. The AC'97 controller should also drive SYNC and SDATA_OUT low after programming the Si3038 to this low-power mode. When the Si3038 has been instructed to halt BIT_CLK, a special wake up protocol must be used to bring the AC-link to the active mode because normal audio output and input frames cannot be communicated in the absence of BIT_CLK.
Note: The Si3038's PLL must be initialized before being placed in sleep mode. PLL is initialized by writing a sample rate in register 40h (42h).
Waking Up the AC-Link There are two methods for bringing the AC-link out of a low-power, halted mode. Regardless of the method, the AC'97 controller performs the wake-up task. AC-link protocol provides for a cold reset and a warm
Rev. 2.01
Si3038
Control Registers
Note: Any register not listed here is reserved and should not be written. Undefined/unimplemented registers return 0.
Table 26. Register Summary
Register Name 3Ch 3Eh 40h 42h 46h 48h 4Ch 4Eh 50h 52h 54h 56h
Extended Modem ID Extended Modem Status & Control Line 1 DAC/ ADC Rate Line 2 DAC/ ADC Rate Line 1 DAC/ ADC Level Line 2 DAC/ ADC Level GPIO Pin Configuration GPIO Pin Polarity & Type GPIO Pin Sticky GPIO Pin Wake Up Mask GPIO Pin Status Miscellaneous Modem AFE Status & Control Chip ID & Revision Line Side Configuration 1 Line Side Status Line Side Configuration 2 Line Side Configuration 3 Vendor ID Register Vendor ID Register F7 T7 F6 T6 F5 T5 F4 T4 F3 T3 F2 T2 F1 T1 F0 T0 S7 PID2 S6 PID1 S5 PID0 S4 S3 ARM1 ARM0 ATM1 ATM0 IIRE SQLCH RFWE SR15 SR15 Mute Mute GC15 GP15 GC14 GP14 GC13 GP13 GC12 GP12 SR14 SR14
D15 D14 D13 D12 D11 D10
ID1 ID0 PRF PRE PRD PRC
D9
D8
D7
D6
D5
D4
D3
D2
D1
LIN2
D0
LIN1 GPIO
PRB
PRA
DAC2
ADC2
DAC1
ADC1
MREF
SR13 SR13
SR12 SR12
SR11 SR11 DAC3 DAC3 GC11 GP11
SR10 SR10 DAC2 DAC2 GC10 GP10
SR9 SR9 DAC1 DAC1
SR8 SR8
SR7 SR7 Mute Mute
SR6 SR6
SR5 SR5
SR4 SR4
SR3 SR3 ADC3 ADC3
SR2 SR2 ADC2 ADC2 GC2 GP2
SR1 SR1 ADC1 ADC1 GC1 GP1
SR0 SR0
GC5 GP5
GC4 GP4
GC3 GP3
GC0 GP0
GS15
GS14
GS13
GS11 GW11
GS5 GW5
GS4 GW4
GS3 GW3
GS1 GW1
GW15 GW14 GW13
GI15
GI14
GI13
GI12 MLNK
GI11
GI10 L2B2
GI5 L2B1
GI4 L2B0
GI3
GI2 L1B2
GI1 L1B1
GI0 L1B0
5Ah 5Ch 5Eh 62H 64h 7Ch 7Eh
CBID
REVB3
REVB2
REVB1
REVB0
REVA3
REVA2
REVA1
REVA0
OHS
BTE
ACT
DCT1
DCT0
RZ
RT
PDC
ROV
BTD DIAL
CLE FJM
FDT VOL1
LCS3 VOL0
LCS2 LIM1
LCS1 LIM0
LCS0
RDTP
RDTN
OVL
S2
S1
S0
38
Rev. 2.01
Si3038
Register 3Ch Extended Modem ID D15
ID1
D14
ID0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LIN2
D0
LIN1
Reset settings (dependent on pins ID1 and ID0) = 0001 8002 4001 Cxxx Bit 15 14 13:2 1 0 Name ID1 ID0 Reserved LIN2 LIN1 Function ID1, ID0 is a 2-bit field which indicates the Codec configuration: Primary is 00; Secondary is 01 and 10; Factory Test is 11 Read returns zero. LIN2 = 1 indicates 2nd line is supported, ID1:0 = 10. Codec Data is transferred in slot 10. LIN1 = 1 indicates 1st line is supported, ID1:0 = 01. Codec Data is transferred in slot 5.
Rev. 2.01
39
Si3038
Register 3Eh Extended Modem Status and Control D15 D14 D13
PRF
D12
PRE
D11
PRD
D10
PRC
D9
PRB
D8
PRA
D7
D6
D5
D4
D3
D2
D1
D0
DAC2 ADC2 DAC1 ADC1 MREF GPIO
Reset settings = 0xFF00 Bits 7-0 are read only, 1 indicates modem AFE subsystem readiness. Bits 13-8 are read/write and control modem AFE subsystem power-down. Note: When bits 13-8 are all set to 1, the Si3014 is powered down. Bit 15:14 13 12 11 10 9 8 7:6 5 4 3 2 1 0 Name Reserved PRF PRE PRD PRC PRB PRA Reserved DAC2 ADC2 DAC1 ADC1 MREF GPIO Read returns one. PRF = 1 indicates Modem Line 2 DAC off. PRE = 1 indicates Modem Line 2 ADC off. PRD = 1 indicates Modem Line 1 DAC off. PRC = 1 indicates Modem Line 1 ADC off. Reserved for future use. PRA = 1 indicates GPIO power-down. Read returns zero. DAC2 = 1 indicates Modem Line 2 DAC ready. ADC2 = 1 indicates Modem Line 2 ADC ready. DAC1 = 1 indicates Modem Line 1 DAC ready. ADC1 = 1 indicates Modem Line 1 ADC ready. MREF = 1 indicates Modem VREF is up to nominal level. GPIO = 1 indicates GPIO ready. Function
40
Rev. 2.01
Si3038
Register 40h Line 1 DAC/ADC Rate D15
SR15
D14
SR14
D13
SR13
D12
SR12
D11
SR11
D10
SR10
D9
SR9
D8
SR8
D7
SR7
D6
SR6
D5
SR5
D4
SR4
D3
SR3
D2
SR2
D1
SR1
D0
SR0
Reset settings = 0x0000 Each DAC/ADC pair is governed by a read/write modem sample rate control register that contains a 16-bit unsigned value between 0 and 65535, representing the rate of operation in Hz. A number written over 0x3592 will cause the sample rate to be 13.714 kHz. For all rates, if the value written to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned. When set to zero, the internal PLL is disabled. The PLL should be programmed before the line side (Si3014) is activated via clearing any PR bit in register 3Eh. Furthermore, sleep mode is not supported when the PLL is disabled. Sample rates for Line 1 and Line 2 Sample Rate 7200 8000 8228.57 (57600/7) 8400 9000 9600 10285.71 (72000/7) 12000 13714.28 (96000/7) D15-D0 1C20 1F40 2024 20D0 2328 2580 282D 2EE0 3592
Register 42h Line 2 DAC/ADC Rate D15
SR15
D14
SR14
D13
SR13
D12
SR12
D11
SR11
D10
SR10
D9
SR9
D8
SR8
D7
SR7
D6
SR6
D5
SR5
D4
SR4
D3
SR3
D2
SR2
D1
SR1
D0
SR0
Reset settings = 0x0000 (rates same as for Line 1, refer to above table)
Rev. 2.01
41
Si3038
Register 46h Line 1 DAC/ADC Level D15
Mute
D14
D13
D12
D11
D10
D9
D8
D7
Mute
D6
D5
D4
D3
D2
D1
D0
DAC3 DAC2 DAC1
ADC3 ADC2 ADC1
Reset setting for Line 1 device = 0x8080 Reset setting for Line 2 device = 0x0000 This read/write register controls the modem AFE DAC and ADC levels. The default value after cold register reset for this register (8080h) corresponds to 0 dB DAC attenuation with mute on and 0 dB ADC gain with mute on. Bit 15 Name Mute Transmit Mute. 0 = mute off. 1 = mute on. Read returns zero. Analog Transmit Attenuation. 000 = 0 db attenuation. 001 = 3 db attenuation. 010 = 6 db attenuation. 011 = 9 db attenuation. 1xx = 12 db attenuation. Read returns zero. Receive Mute. 0 = mute off. 1 = mute on. Read returns zero. Analog Receive Gain. 000 = 0 db gain. 001 = 3 db gain. 010 = 6 db gain. 011 = 9 db gain. 1xx = 12 db gain. Read returns zero. Function
14:12 11:9
Reserved DAC[3:1]
8 7
Reserved Mute
6:4 3:1
Reserved ADC[3:1]
0
Reserved
42
Rev. 2.01
Si3038
Register 48h Line 2 DAC/ADC Level D15
Mute
D14
D13
D12
D11
D10
D9
D8
D7
Mute
D6
D5
D4
D3
D2
D1
D0
DAC3 DAC2 DAC1
ADC3 ADC2 ADC1
Reset setting for Line 1 device = 0x0000 Reset setting for Line 2 device = 0x8080 This read/write register controls the modem AFE DAC and ADC levels. The default value after cold register reset for this register (0x8080) corresponds to 0 db DAC attenuation with mute on and 0 db ADC gain with mute on. Bit 15 Name Mute Function Transmit Mute. 0 = mute off. 1 = mute on. Read returns zero. Analog Transmit Attenuation. 000 = 0 db attenuation. 001 = 3 db attenuation. 010 = 6 db attenuation. 011 = 9 db attenuation. 1xx = 12 db attenuation. Read returns zero. Receive Mute. 0 = mute off. 1 = mute on. Read returns zero. Analog Receive Gain. 000 = 0 db gain. 001 = 3 db gain. 010 = 6 db gain. 011 = 9 db gain. 1xx = 12 db gain. Read returns zero.
14:12 11:9
Reserved DAC[3:1]
8 7
Reserved Mute
6:4 3:1
Reserved ADC[3:1]
0
Reserved
Register 4Ch GPIO Pin Configuration D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
GC5
D4
GC4
D3
GC3
D2
GC2
D1
GC1
D0
GC0
GC15 GC14 GC13 GC12 GC11 GC10
Reset setting for Line 1 device = 0x003F Reset setting for Line 2 device = 0xFC00 The GPIO Pin Configuration register is read/write for configuring Slot 12 I/O. These pins are digital commands (virtual pins). This register specifies whether a GPIO pin is configured for input (1) or output (0). The digital controller sends the desired GPIO pin value over output slot 12 in the outgoing stream of the AC-link before configuring any of these bits for output.
Rev. 2.01
43
Si3038
Register 4Eh GPIO Pin Polarity and Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
GP5
D4
GP4
D3
GP3
D2
GP2
D1
GP1
D0
GP0
GP15 GP14 GP13 GP12 GP11 GP10
Reset settings = 0xFFFF The GPIO Pin Polarity/Type register is read/write for selecting the polarity and type for Slot 12 I/O. This register defines GPIO Input Polarity (0 = low, 1 = high active) when a GPIO pin is configured as an input. It defines GPIO output type (0 = CMOS, 1 = OPEN-DRAIN) when a GPIO pin is configured as an output. The default value after soft reset (FFFFh) is all pins active high. Non-implemented GPIO pins always return 1s.
Note: Register 4Eh is not effected by a cold or warm reset. (This is to avoid corrupting Sticky bits.)
Register 50h GPIO Pin Sticky D15 D14 D13 D12 D11
GS11
D10
D9
D8
D7
D6
D5
GS5
D4
GS4
D3
GS3
D2
D1
GS1
D0
GS15 GS14 GS13
Reset settings = 0x0000 The GPIO Pin Sticky is a read/write register. It defines the GPIO input type (0 = Non-Sticky, 1 = Sticky) when a GPIO pin (defined in slot 12 I/O) is configured as an input. Applies to Ring Detect, Delta Loop Current Sense, GPIO_A, and GPIO_B bits. GPIO inputs configured as Sticky are cleared only by writing a 0 to the corresponding bit of the GPIO Pin Status Register 54h. The default value after cold register reset (0000h) is all pins Non-Sticky. Unimplemented GPIO pins always return zeros. Sticky is defined as Edge sensitive; Non-Sticky is defined as Level sensitive. Register 52h GPIO Pin Wake Up Mask D15 D14 D13 D12 D11
GW11
D10
D9
D8
D7
D6
D5
GW5
D4
GW4
D3
GW3
D2
D1
GW1
D0
GW15 GW14 GW13
Reset settings = 0x0000 The GPIO Pin Wake-up is a read/write register that provides a mask for determining if an input GPIO change will generate a wake-up or GPIO_INT (0 = No, 1 = Yes). When the AC-link is powered down, a wake-up event will trigger the assertion of SDATA_IN. When AC-link is powered up, a wake-up event will appear as GPIO_INT = 1 on bit 0 of input slot 12. Ring-detection wake-up can be enabled or disabled. An AC-Link wake-up interrupt is defined as a 0 to 1 transition on SDATA_IN when the AC-link is powered down. GPIO bits that have been programmed as Inputs, Sticky, and Pin Wake-up, upon transition (either high-to-low or low-to-high) depending on pin polarity, will cause an AC-Link wake-up event, if the AC-Link was powered down. The default value after cold register reset (0000h) defaults to all 0s specifying no wake-up event. Applies to Ring Detect, Delta Loop Current Sense, GPIO_A, and GPIO_B bits. Non-implemented GPIO pins always return 0s.
44
Rev. 2.01
Si3038
Register 54h GPIO Pin Status D15
GI15
D14
GI14
D13
GI13
D12
GI12
D11
GI11
D10
GI10
D9
D8
D7
D6
D5
GI5
D4
GI4
D3
GI3
D2
GI2
D1
GI1
D0
GI0
Reset settings = 0xxxxx GPIO Status is a read/write register that reflects the state of all GPIO pins (inputs and outputs) on slot 12. The value of all GPIO pin inputs and outputs comes from each frame on slot 12, but is also available for reading as GPIO Pin Status via the standard slot 1 and 2 command address/data protocols. GPIO inputs configured as Sticky are cleared by writing a 0 to the corresponding bit of this register. (This should be the last event before setting the AC'97 MLNK bit.) Bits corresponding to unimplemented GPIO pins should be forced to zero in this register and input slot 12. GPIO bits that have been programmed as Inputs and Sticky, upon transition (high-to-low or low-to-high), will cause the individual GI bit to go asserted 1, and remain asserted until a write of 0 to that bit. The only way to set the desired value of a GPIO output pin is to set the control bit in output slot 12. If configured as an input, the default value after register reset is always the state of the GPIO pin.
Rev. 2.01
45
Si3038
Register 56h Miscellaneous Modem AFE Status and Control D15 D14 D13 D12
MLNK
D11
D10
D9
D8
D7
D6
L2B2
D5
L2B1
D4
L2B0
D3
D2
L1B2
D1
L1B1
D0
L1B0
Reset settings = 0x0000 This read/write register defines the loopback modes available for the modem line ADCs/DACs. The default value after cold register reset (0xx000) is all loopbacks disabled.
'
Bit 15:13 12 11:7 6:4
Name Reserved MLNK Reserved L2B[2:0] Read returns zero.
Function Controls an MC`97's AC-link status. 1 sets the MC`97's AC-link to off (sleep), 0 sets the link on (active). Read returns zero. Line 2 Loopback Modes. 000 = Disabled (default). 001 = ADC Loopback (IB). 010 = Local Analog Loopback (FM). 011 = Digital DAC Loopback (CJ). 100 = Remote Analog Loopback (MF). 101 = ISOcap Loopback (DK). 110 = External Analog Loopback (GN). 111 = Reserved. Read returns zero. Line 1 Loopback Modes. 000 = Disabled (default). 001 = ADC Loopback (IB). 010 = Local Analog Loopback (FM). 011 = Digital DAC Loopback (CJ). 100 = Remote Analog Loopback (MF). 101 = ISOcap Loopback (DK). 110 = External Analog Loopback (GN). 111 = Reserved.
3 2:0
Reserved L1B[2:0]
3024 A AC Link H B I Digital Filter Digital Filter C J D K Analog DAC Analog ADC
3014 E L F M I/O Pad I/O Pad DAC O utput ADC Input G N
Note: For all loopback m odes except 011, line-side m ust be powered on and off-hook.
Figure 33. Loopback Points
46
Rev. 2.01
Si3038
Register 5Ah Chip ID and Revision D15 D14 D13 D12 D11 D10 D9 Reset settings = n/a Bit 15:9 8 Name Reserved CBID Read returns zero. Chip B (line side) ID. 0 = Line-side is domestic. 1 = Line-side has international support. Function D8 D7 D6 D5 D4 D3 D2 D1 D0
CBID REVB3 REVB2 REVB1 REVB0 REVA3 REVA2 REVA1 REVA0
7:4
REVB[3:0] Chip Revision. Four-bit value indicating the revision of the Si3014 (line side) silicon. 0010 = Si3014 Rev B. 0011 = Si3014 Rev C. REVA[3:0] Chip Revision. Four-bit value indicating the revision of the Si3024 (system-side) silicon. 0010 = Si3024 Rev B. 0011 = Si3024 Rev C.
3:0
Note: Line-side must be activated via PR bits before valid read.
Rev. 2.01
47
Si3038
Register 5Ch Line Side Configuration 1 D15
ARM1
D14
ARM0
D13
D12
D11
IIRE
D10
D9
D8
D7
OHS
D6
BTE
D5
ACT
D4
D3
D2
RZ
D1
D0
RT
ATM1 ATM0
SQLCH RFWE
DCT1 DCT0
Reset settings = 0xF010 Bit 15:14 Name ARM[1:0] Function Analog (Call Progress) Receive Path Mute. 00 = 0 dB. 01 = -6 dB. 10 = -12 dB. 11 = mute. Analog (Call Progress) Transmit Path Mute. 00 = -20 dB. 01 = -26 dB. 10 = -32 dB. 11 = mute. IIR Filter Enable. 0 = FIR filter enabled for transmit and receive filters. (See Figures 9-12 on page 13.) 1 = IIR filter enabled for transmit and receive filters. (See Figures 13-18 on page 14.) Ring Detect Network Squelch. This bit must be set, then cleared, following a polarity reversal detection. Used to quickly recover the offset on the RNG1/2 pins after a polarity reversal. 0 = Normal. 1 = Squelch. Ring Detector Full Wave Rectifier Enable. When set, the ring detection circuitry provides full wave rectification. This will effect the data stream presented on SDATA_IN during ring detection. 0 = Half Wave. 1 = Full Wave. Read returns zero. On-Hook Speed. Sets speed of execution of an on-hook. 0 = Fast. 1 = Slow. Billing Tone Detector Enable. When set, a billing tone signal is detected on the line and off-hook is maintained through the billing tone. If a billing tone is detected, the BTD bit of register 5Eh will be set to indicate the event.
13:12
ATM[1:0]
11
IIRE
10
SQLCH
9
RFWE
8 7
Reserved OHS
6
BTE
48
Rev. 2.01
Si3038
Bit 5 Name ACT AC Termination Select. 0 = Selects the real impedance. 1 = Selects the complex impedance. DC Termination Select. 00 = Reserved. 01 = Japan Mode. Low voltage mode. (Transmit level = -3 dBm). 10 = FCC Mode. Standard voltage mode. (Transmit level = -1 dBm). 11 = CTR21 Mode. Current limiting mode. (Transmit level = -1 dBm). Ringer Impedance. 0 = Maximum (high) ringer impedance. 1 = Synthesize ringer impedance. C15, R14, Z2, and Z3 must not be installed when setting this bit. See "Ringer Impedance" on page 25. Read returns zero. Ringer Threshold Select. Used to satisfy country requirements on ring detection. Signals below the lower level will not generate a ring detection. Signals above the upper level are guaranteed to generate a ring detection. 0 = 11 to 22 VRMS. 1 = 17 to 33 VRMS. Function
4:3
DCT[1:0]
2
RZ
1 0
Reserved RT
Rev. 2.01
49
Si3038
Register 5Eh Line Side Status D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
LCS3
D4
LCS2
D3
D2
D1
RDTP
D0
RDTN
PDC ROV BTD CLE FDT Reset setting = 0x0000 Bit 15:11 10 9 Name Reserved PDC ROV Read returns zero.
LCS1 LCS0
Function
Charge Pump Disable. This bit disables the internal charge pump when set. Receive Overload. This bit is set when the receive input detects an excessive input level. A write of zero is required to clear this bit. (This bit is disabled when BTE = 0 in Register 5Ch.) Billing Tone Detected. This bit will be set if BTE bit of register 5Ch is enabled and a billing tone is detected. A write of zero is required to clear this bit. (This bit is only active when BTE = 1 in Register 5Ch.) Communications (ISOcap) Error. 1 = Indicates a communication problem between the Si3024 and Si3014. When it goes high, it remains high until a logic 0 is written to it. Frame Detect. 0 = Indicates ISOcap communication has not established frame lock. 1 = Indicates ISOcap frame lock has been established. Loop Current Sense. Four-bit value returning the loop current in 6 mA increments. 0 = Loop current < 0.4 mA typical 1111 = Loop current > 155 mA typical. See "Loop Current Monitor" on page 28. Ring Detect Signal Positive. 1 = Positive ring signal is occurring. Ring Detect Signal Negative. 1 = Negative ring signal is occurring.
8
BTD
7
CLE
6
FDT
5:2
LCS[3:0]
1 0
RDTP RDTN
Note: Line-side must be activated via PR bits before valid read/write.
50
Rev. 2.01
Si3038
Register 62h Line Side Configuration 2 D15 D14 D13 D12 D11 D10 D9 D8
DIAL
D7
FJM
D6
D5
D4
D3
LIM0
D2
D1
D0
VOL1 VOL0 LIM1
Reset setting = 0x0000 Bit 15:9 8 Name Reserved DIAL Read returns zero. DTMF Dialing Mode. This bit should be set during DTMF dialing in CTR21 mode if LCS[3:0] < 6. 0 = Normal operation. 1 = Increase headroom for DTMF dialing. Force Japan DC Termination Mode. 0 = Normal Gain 1 = When register 16, DCT[1:0], is set to 10b (FCC Mode), setting this bit will force Japan dc termination mode while allowing for a transmit level of -1 dBm. See "DTMF Dialing" on page 26. Line Voltage Adjust. When set, this bit will adjust the TIP-RING line voltage. Lowering this voltage will improve margin in low voltage countries. Raising this voltage may improve distortion performance. 00 = Normal. 01 = -0.125 V. 10 = 0.25 V. 11 = 0.125 V. Current Limit. 00 = All other modes. 11 = CTR21 mode. Read returns zero. Function
7
FJM
6:5
VOL[1:0]
4:3
LIM[1:0]
2:0
Reserved
Rev. 2.01
51
Si3038
Register 64h Line Side Configuration 3 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
BTM
D1
D0
Reset setting = 0x0000 Bit 15:8 7 6:3 2 Name Reserved Reserved Reserved OVL Read returns zero. Read returns zero or one. Read returns zero. Overload Detected. This bit has the same function as ROV in register 5E but will clear itself after the overload has been removed. See "Billing Tone Detection" on page 26. Test bits. Function
1:0
Reserved
Register 7Ch and 7Eh Vendor ID Registers D15
F7 T7
D14
F6 T6
D13
F5 T5
D12
F4 T4
D11
F3 T3
D10
F2 T2
D9
F1 T1
D8
F0 T0
D7
S7 PID2
D6
S6 PID1
D5
S5 PID0
D4
S4
D3
S3
D2
S2
D1
S1
D0
S0
Reset settings F[7:0] = 53h S[7:0] = 49h T[7:0] = 4Ch PID[2:0] = 001b Remaining Bits = Reserved These registers are for specific vendor identification. The ID method is Microsoft's Plug and Play Vendor ID code with F7..0 being the first character of that ID, S7..0 being the second character, and T7..0 the third character. These three characters are ASCII encoded. Silicon Laboratories Vendor ID is "SIL" or "53h 49h 4Ch". The PID[2:0] field contains the Silicon Laboratories Part ID ("001b").
52
Rev. 2.01
Si3038 APPENDIX A-- UL 1950 3RD ED I T I O N
Designs using the Si3038 pass all overcurrent and overvoltage tests for UL1950 3rd Edition compliance with a couple of considerations. Figure 34 shows the designs that can pass the UL1950 overvoltage tests, as well as electromagnetic emissions. The top schematic of Figure 34 shows the configuration in which the ferrite beads (FB1, FB2) are on the unprotected side of the sidactor (RV1). For this configuration, the current rating of the ferrite beads needs to be 6 A. However, the higher current ferrite beads are less effective in reducing electromagnetic emissions. The bottom schematic of Figure 34
C24 75 @ 100 MHz, 6 A 1.25 A FB1 TIP
configuration in which the ferrite beads (FB1, FB2) are on the protected side of the sidactor (RV1). For this design, the ferrite beads can be rated at 200 mA. In a cost optimized design, it is important to remember that compliance to UL1950 does not always require overvoltage tests. It is best to plan ahead and know which overvoltage tests will apply to your system. System-level elements in the construction, such as fire enclosure and spacing requirements, need to be considered during the design stages. Consult with your Professional testing agency during the design of the product to determine which tests apply to your system.
shows
the
RV1
75 @ 100 MHz, 6 A FB2 RING
C25
C24 600 @ 100 M Hz, 200 m A FB1 1.25 A TIP
RV1 FB2 RING 600 @ 100 M Hz, 200 m A
C25
Figure 34. Circuits that Pass all UL1950 Overvoltage Tests
Rev. 2.01 53
Si3038 APPENDIX B--CISPR22 COMPLIAN C E
Various countries are expected to adopt the IEC CISPR22 standard over the next few years. For example, the European Union (EU) has adopted a standard entitled EN55022, which is based on the CISPR22 standard. EN55022 is now part of the EU's EMC Directive and compliance is expected to be required starting in 2003. Adherence to this standard will be necessary to display the CE mark on designs intended for sale in the EU. The typical schematic and global bill of materials (BOM) (see Figure 19 and Table 16) contained in this data sheet are designed to be compliant to the CISPR22 standard. If smaller inductors are desired, a notch filter may be used and compliance to CISPR22 still achieved. As shown in Figure 35, a series capacitor-resistor in parallel with L1 and L2 forms the simple notch filter. Table 27 shows corresponding values used for C24, C25, C38, C39, L1, L2, R31, and R32.
C38 R31
The direct current resistance (DCR) of the listed inductors is an important consideration. If the DCR of the inductors used is less than 3 each, then country PTT specifications which require 300 or less of dc resistance at TIP and RING with 20 mA of loop current can be satisfied with the Japan dc termination mode. If the DCR of the inductors is at or slightly above 3 , the low voltage termination mode may need to be used to satisfy the 300 dc resistance requirement at 20 mA of loop current. In all cases, "DC Termination Considerations" on page 24 should be followed. If compliance to the CISPR22 standard and certain other country PTT requirements are not desired, then L1 and L2 may be removed. If these inductors are removed, C24 and C25 should be increased to 2200 pF, and C9 should be changed to 22 nF, 250 V. With these changes, PTT compliance in the following countries will not be achieved: India (I/Fax-03/03 standard), Taiwan (ID0001 standard), Chile (Decree No. 220 1981 standard), and Argentina (CNC-St2-44.01 standard). For questions concerning compliance to CISPR22 or other relevant standards, contact a Silicon Laboratories technical representative.
L1 C24 To DAA
FB1
TIP
C39
R32
L2 C25
FB2
RING
Figure 35. Notch Filter for CISPR22 Compliance Table 27. Notch Filter Component Values
C24/C25 C38/C39 1000 pF 33 pF, 50 V L1/L2 150 H, DCR < 3 , I > 120 mA R31/R32 680 , 1/10 W
54
Rev. 2.01
Si3038
Pin Descriptions: Si3024
Si3024 (SOIC)
MCLK/XIN XOUT BIT_CLK VD SDA TA _IN SDA TA _OUT SY NC RESET 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GPIO_A GPIO_B ID1 VA GND C1A ID0 A OUT
Si3024 (TSSOP)
SDATA_IN SDATA_OUT SYNC RESET AOUT ID0 C1A GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VD BIT_CLK XOUT MCLK/XIN GPIO_A GPIO_B ID1 VA
Table 28. 3024 Pin Descriptions
SOIC Pin # 1 2 3 TSSOP Pin # 13 14 15 Pin Name MCLK/XIN XOUT BIT_CLK Master clock Input/Crystal In. Crystal Output. Serial Port Bit Clock Output/Input. Controls the serial data on SDATA_IN and latches the data on SDATA_OUT. Output when configured as primary device. Input when configured as secondary device. 4 16 VD Digital Power Supply. Provides the digital supply voltage to the Si3024. Nominally either 5 V or 3.3 V. 5 1 SDATA_IN AC-Link Serial Data In. Serial communication and status data that is provided by the Si3024 to the digital AC'97 controller. 6 2 SDATA_OUT AC-Link Serial Data Out. Serial communication and control data that is generated by the digital AC'97 controller and presented as an input to the Si3024. 7 3 SYNC Frame Sync Input. Data framing signal that is used to indicate the start and stop of a communication data frame. 8 4 RESET Reset Input. An active low input that is used to reset all control registers to a defined, initialized state. Also used to bring the Si3036 out of sleep mode. 9 10 11 12 5 6 7 8 AOUT ID0 C1A GND Analog Speaker Output. Provides an analog output signal for driving a call progress speaker. Device ID Bit 0. Bit 0 of the device configuration. Internal pull-up to VDD. Isolation Capacitor 1A. Connects to one side of the isolation capacitor C1. Ground. Connects to the system digital ground. Also connects to capacitor C2. Description
Rev. 2.01
55
Si3038
Table 28. 3024 Pin Descriptions (Continued)
SOIC Pin # 13 14 15 16 TSSOP Pin # 9 10 11 12 Pin Name VA ID1 GPIO_B GPIO_A Analog Supply Voltage. Provides the analog supply voltage for the Si3024. Nominally 5 V. Device ID Bit 1. Bit 1 of the device configuration. Internal pull-up to VDD. General Purpose I/O B. Programmable via registers 4Ch-54h. Default input. General Purpose I/O A. Programmable via registers 4Ch-54h. Default input. Description
56
Rev. 2.01
Si3038
Pin Descriptions--Si3014
QE2 DCT IGND C1B RNG1 RNG2 QB QE
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
FILT2 FILT RX REXT REXT2 REF V REG2 V REG
Table 29. 3014 Pin Descriptions
Pin # 1 2 3 4 5 Pin Name QE2 DCT IGND C1B RNG1 Transistor Emitter 2. Connects to the emitter of Q4. DC Termination. Provides dc termination to the telephone network. Isolated Ground. Connects to ground on the line-side interface. Also connects to capacitor C2. Isolation Capacitor 1B. Connects to one side of isolation capacitor C1. Ring 1. Connects through a capacitor to the TIP lead of the telephone line. Provides the ring and caller ID signals to the Si3038. 6 RNG2 Ring 2. Connects through a capacitor to the RING lead of the telephone line. Provides the ring and caller ID signals to the Si3038. 7 8 9 10 11 12 13 QB QE VREG VREG2 REF REXT2 REXT Transistor Base. Connects to the base of transistor Q3. Transistor Emitter. Connects to the emitter of transistor Q3. Voltage Regulator. Connects to an external capacitor to provide bypassing for an internal power supply. Voltage Regulator 2. Connects to an external capacitor to provide bypassing for an internal power supply. Reference. Connects to an external resistor to provide a high accuracy reference current. External Resistor 2. Sets the complex ac termination impedance. External Resistor. Sets the real ac termination impedance. Description
Rev. 2.01
57
Si3038
Table 29. 3014 Pin Descriptions (Continued)
Pin # 14 15 16 Pin Name RX FILT FILT2 Receive Input. Serves as the receive side input from the telephone network. Filter. Provides filtering for the dc termination circuits. Filter 2. Provides filtering for the bias circuits. Description
58
Rev. 2.01
Si3038
Ordering Guide
Table 30. Ordering Guide
Chipset Si3034 Si3035 Si3036 Si3038 Si3044 Si3044 Si3046 Si3048 Region Global FCC/Japan FCC/Japan Global Enhanced Global Enhanced Global FCC/JATE Global Interface DSP Serial I/F DSP Serial I/F AC Link AC Link DSP Serial I/F DSP Serial I/F AC Link AC Link Digital (SOIC) SI3021-KS SI3021-KS Si3024-KS Si3024-KS SI3021-KS Si3021-BS Si3025-KS Si3025-KS Line (SOIC) Si3014-KS Si3012-KS Si3012-KS Si3014-KS Si3015-KS Si3015-BS Si3012-KS Si3014-KS Digital (TSSOP) Si3021-KT Si3021-KT Si3024-KT Si3024-KT Line (TSSOP) Si3014-KT Si3012-KT Si3012-KT Si3014-KT Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C 0C to 70C 0C to 70C
Rev. 2.01
59
Si3038
SOIC Outline
Figure 36 illustrates the package details for the Si3024 and Si3014. Table 31 lists the values for the dimensions shown in the illustration.
16 9 h E H 0.010
GA UGE PLA NE L Detail F
1
B
8
D
A2 e A1
A
C L1 See Detail F
Seating Plane
Figure 36. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 31. Package Diagram Dimensions
Symbol A A1 A2 B C D E e H h L L1 Millimeters Min Max 1.35 1.75 .10 .25 1.30 1.50 .33 .51 .19 .25 9.80 10.01 3.80 4.00 1.27 BSC -- 5.80 6.20 .25 .50 .40 1.27 1.07BSC -- -- 0.10 0 8
60
Rev. 2.01
Si3038
TSSOP Outline
Figure 37 illustrates the package details for the Si3024 and Si3014. Table 32 lists the values for the dimensions shown in the illustration.
E1
E
2
R1 R
1
S
L L1
e
3
D
A2
A
c
b A1
Figure 37. 16-pin Thin Small Shrink Outline Package (TSSOP) Table 32. Package Diagram Dimensions
Symbol A A1 A2 b c D e E E1 L L1 R R1 S 1 2 3 Min -- 0.05 0.80 0.19 0.09 4.85 Millimeters Nom 1.10 -- 1.00 -- -- 5.00 0.65 BSC 6.40 BSC 4.40 0.60 1.00 REF -- -- -- -- 12 REF 12 REF Max 1.20 0.15 1.05 0.30 0.20 5.15
4.30 0.45 0.09 0.09 0.20 0
4.50 0.75 -- -- -- 8
Rev. 2.01
61
Si3038
Rev 1.0 to Rev 1.1 Change List
Typical Application Circuit was updated. C24, C25 value changed from 470 pF to 1000 pF and C31, C32 were added in Table 16 and Table 17. In Table 17, the tolerance was also changed from 20% to 10%.
Rev 1.1 to Rev 1.2 Change List
TSSOP information added. Added note to Table 2. Amended note 3 in Table 5. Added China settings to Table 19. Added "DC Termination Considerations." Figure 19, "Typical Applications Circuit for the Dual Design Si3036 and Si3038," on page 16 updated. Table 16, "Global Component Values--Si3038 Chipset," on page 17 updated. Table 17, "FCC Component Values--Si3036 Chipset," on page 18 updated.
Rev 1.2 to Rev 2.0 Change List
Updated applications schematic (Figure 19) and BOM (tables 16 and 17). Added Appendix B. Corrected transmit frequency response specification to 0 Hz typical. Updated "Overload Detection" section text concerning CTR21 mode. Removed CTRO bit (Register 64h, bit 7). Updated Singapore DCT setting to DCT[1:0] = 10 in Table 19. Updated initialization section sequence (third item) to "Write 0x0000 to register 3Eh..."
Rev 2.0 to Rev 2.01 Change List
Table 19 updated. "Appendix B--CISPR22 Compliance" updated. The "Ringer Impedance Network" figure and the "Component Values--Optional Ringer Impedance Network" table were deleted from the "Ringer Impedance" section as well as a paragraph discussing Czech Republic designs. The "Dongle Applications Circuit" figure was deleted.
62
Rev. 2.01
Si3038 NOTES:
Rev. 2.01
63
Si3038
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ISOcap are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
64
Rev. 2.01

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